SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
UART PowerManagement and Emulation Register.
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| Instance Name | Physical Address |
|---|---|
| ICSSM0 | 4802 8030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | UTRST | URRST | RESERVED | ||||
| R/W | R/W | R/W | NONE | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | FREE | |||||
| NONE | R | R/W | |||||
| 0h | 1h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | RESERVED | R/W | 0h | Reserved |
| 14 | UTRST | R/W | 0h | UART transmitter reset. Resets and enables the transmitter. 1 Transmitter is enabled. 0 Transmitter is disabled and in reset state. |
| 13 | URRST | R/W | 0h | UART receiver reset. Resets and enables the receiver. 1 Receiver is enabled. 0 Receiver is disabled and in reset state. |
| 12:2 | RESERVED | NONE | 0h | Reserved |
| 1 | RESERVED | R | 1h | Reserved |
| 0 | FREE | R/W | 0h | Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events. 1 Free-running mode is enabled; UART
continues to run normally.
0 If a transmission is not in progress, the
UART halts immediately. If a transmission
is in progress, the UART halts after
completion of the one-word transmission. |