SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Enable Clear Register 0
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| Instance Name | Physical Address |
|---|---|
| ICSSM0 | 4810 00C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PR1_RAM_ENABLE_CLR | PR1_PDSP1_IRAM_ENABLE_CLR | PR1_PDSP0_IRAM_ENABLE_CLR | PR1_DRAM1_ENABLE_CLR | PR1_DRAM0_ENABLE_CLR | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | PR1_RAM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pr1_ram_pend |
| 3 | PR1_PDSP1_IRAM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pr1_pdsp1_iram_pend |
| 2 | PR1_PDSP0_IRAM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pr1_pdsp0_iram_pend |
| 1 | PR1_DRAM1_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pr1_dram1_pend |
| 0 | PR1_DRAM0_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pr1_dram0_pend |