SPRUJ73 December   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
  6. 2Hardware Description
    1. 2.1 Component Identification
    2. 2.2 Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
    3. 2.3 Functional Block Diagram
    4. 2.4 Header Information
    5. 2.5 Interfaces
      1. 2.5.1 ADC
      2. 2.5.2 LIN
      3. 2.5.3 MCAN
      4. 2.5.4 TRACE/GPMC Muxing Scheme
      5. 2.5.5 GPMC Memory Interface
        1. 2.5.5.1 PSRAM
        2. 2.5.5.2 GPMC Memory Footprint
        3. 2.5.5.3 NOR FLASH
      6. 2.5.6 TI 14-Pin Header
      7. 2.5.7 MIPI-60 Connector
    6. 2.6 HSEC Pinout
  7. 3Additional Information
    1. 3.1 If You Need Assistance
    2.     Trademarks
  8. 4References
    1. 4.1 Reference Documents
    2. 4.2 Other TI Components Used in This Design
  9. 5Revision History

2.5.5.3 NOR FLASH

The AM263x controlCARD Docking Station design package includes a design for a custom PCB with a MT28EW256ABA NOR FLASH memory module mounted on it. This enables a user to develop using the GPMC0 interface of the AM263x SoC with a NOR FLASH memory module.

GUID-20230111-SS0I-WWTB-BT30-8JFDZVFZSMJW-low.png Figure 2-14 GPMC-NOR FLASH Interface

The GPMC signals originating from the AM263x SoC are passed through the HSEC connector onto the Docking Station. The TRACE/GPMC multiplexing scheme sends the GPMC signals to the GPMC memory footprint, and onto the installed custom MT28EW256ABA NOR FLASH PCB. Refer to Table 3-14 for details on the MUX scheme operation.

All select and enable signals are to be pulled high via 10 kΩ resistors to ensure functionality of the active low signals.

Table 2-17 NOR FLASH Signal Descriptions
AM263x Signal MT28EW256ABA NOR FLASH Signal
GPMC0_A[21:0] GPMC Address Output A[MAX:0] Address
GPMC0_AD[15:0] GPMC Data Input/Output DQ[15:0] Data I/O
GPMC0_CSn0 GPMC Chip Select 0 (active low) C̅E̅ Chip Enable
GPMC0_WEn GPMC Write Enable (active low) W̅E̅ Write Enable
GPMC0_OEn_REn GPMC Output Enable (active low) or Read Enable (active low) O̅E̅ Output Enable
GPMC0_BE0n_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable N/A N/A
GPMC0_BE1n GPMC Upper-Byte Enable (active low) N/A N/A
GPMC0_WAIT0 GPMC External Indication of Wait RY/B̅Y̅ Ready busy
GPMC0_WPn GPMC Flash Write Protect (active low) Vpp/W̅P̅ Vpp/Write Protect
GPIO45 General-Purpose IO 45 B̅Y̅T̅E̅ Byte/word organization select
GPIO46 General-Purpose IO 46 R̅S̅T̅ Reset
GPIO48 General-Purpose IO 48 N/A N/A