SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| DMASS1_INTAGGR_0 | ✓ |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_0 | GICSS0_spi_237 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_0 | WKUP_R5FSS0_CORE0_intr_129 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_0 | MCU_R5FSS0_CORE0_cpu0_intr_129 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_1 | GICSS0_spi_238 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_1 | WKUP_R5FSS0_CORE0_intr_130 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_1 | MCU_R5FSS0_CORE0_cpu0_intr_130 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_2 | GICSS0_spi_239 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_2 | WKUP_R5FSS0_CORE0_intr_131 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_2 | MCU_R5FSS0_CORE0_cpu0_intr_131 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_3 | GICSS0_spi_240 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_3 | WKUP_R5FSS0_CORE0_intr_132 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_3 | MCU_R5FSS0_CORE0_cpu0_intr_132 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_4 | GICSS0_spi_241 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_4 | WKUP_R5FSS0_CORE0_intr_150 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_4 | MCU_R5FSS0_CORE0_cpu0_intr_150 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_5 | GICSS0_spi_242 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_5 | WKUP_R5FSS0_CORE0_intr_158 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_5 | MCU_R5FSS0_CORE0_cpu0_intr_158 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_6 | GICSS0_spi_243 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_6 | WKUP_R5FSS0_CORE0_intr_159 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_6 | MCU_R5FSS0_CORE0_cpu0_intr_159 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_7 | GICSS0_spi_244 | GICSS0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_7 | WKUP_R5FSS0_CORE0_intr_160 | WKUP_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |
| DMASS1_INTAGGR_0 | DMASS1_INTAGGR_0_intaggr_vintr_pend_7 | MCU_R5FSS0_CORE0_cpu0_intr_160 | MCU_R5FSS0_CORE0 | DMASS1_INTAGGR_0 interrupt request | level |