SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| ECAP0 | ✓ | ||
| ECAP1 | ✓ | ||
| ECAP2 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| ECAP0 | PSC0 | GP_CORE | LPSC_main_ip | 34 | ON | YES | LPSC_main_dm2main_infra_iso |
| ECAP1 | PSC0 | GP_CORE | LPSC_main_ip | 34 | ON | YES | LPSC_main_dm2main_infra_iso |
| ECAP2 | PSC0 | GP_CORE | LPSC_main_ip | 34 | ON | YES | LPSC_main_dm2main_infra_iso |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| ECAP0 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock | |
| ECAP1 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock | |
| ECAP2 | FICLK | MAIN_SYSCLK0/4 | functional and interface clock |
| Module Instance | Source | Description |
|---|---|---|
| ECAP0 | PSC0 | ECAP0 reset |
| ECAP1 | PSC0 | ECAP1 reset |
| ECAP2 | PSC0 | ECAP2 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| ECAP0 | ECAP0_ecap_int_0 | GICSS0_spi_145 | GICSS0 | ECAP0 interrupt request | pulse |
| ECAP0 | ECAP0_ecap_int_0 | MCU_R5FSS0_CORE0_cpu0_intr_83 | MCU_R5FSS0_CORE0 | ECAP0 interrupt request | pulse |
| ECAP1 | ECAP1_ecap_int_0 | GICSS0_spi_146 | GICSS0 | ECAP1 interrupt request | pulse |
| ECAP1 | ECAP1_ecap_int_0 | MCU_R5FSS0_CORE0_cpu0_intr_84 | MCU_R5FSS0_CORE0 | ECAP1 interrupt request | pulse |
| ECAP2 | ECAP2_ecap_int_0 | GICSS0_spi_147 | GICSS0 | ECAP2 interrupt request | pulse |
| ECAP2 | ECAP2_ecap_int_0 | MCU_R5FSS0_CORE0_cpu0_intr_85 | MCU_R5FSS0_CORE0 | ECAP2 interrupt request | pulse |