SPRUJH0B April   2025  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 External Power Supply or Accessory Requirements
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Functional Description and Connections
        1. 2.1.1.1 Power Domains
        2. 2.1.1.2 LEDs
        3. 2.1.1.3 Encoder Connectors
        4. 2.1.1.4 Boot Modes
        5. 2.1.1.5 BoosterPack Sites
        6. 2.1.1.6 Analog Voltage Reference
        7. 2.1.1.7 Other Headers and Jumpers
          1. 2.1.1.7.1 USB Isolation Block
          2. 2.1.1.7.2 Alternate Power
          3. 2.1.1.7.3 5V Step-up Converter
        8. 2.1.1.8 Programmable Gain Amplifier (PGA)
      2. 2.1.2 Debug Interface
        1. 2.1.2.1 XDS110 Debug Probe
        2. 2.1.2.2 Virtual COM Port
      3. 2.1.3 Alternate Routing
        1. 2.1.3.1 Overview
        2. 2.1.3.2 GPIO35/GPIO37 Routing
        3. 2.1.3.3 eQEP Routing
        4. 2.1.3.4 X1, X2 Routing
        5. 2.1.3.5 PWM DAC
    2. 2.2 Using the F28E12x LaunchPad
    3. 2.3 BoosterPacks
    4. 2.4 Hardware Revisions
      1. 2.4.1 Revision A
      2. 2.4.2 Revision E2
  9. 3Software
    1. 3.1 Software Development
      1. 3.1.1 Software Tools and Packages
      2. 3.1.2 F28E12x LaunchPad Demo Program
      3. 3.1.3 Programming and Running Other Software on the F28E12x LaunchPad
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 LAUNCHXL-F28E12X Board Dimensions
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Frequently Asked Questions
    2. 5.2 Trademarks
  12. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  13. 7Revision History

2.1.1.6 Analog Voltage Reference

The analog subsystem of the F28E12x allows for flexible voltage reference sources. The ADC modules are referenced to the VREFHIx and VREFLOx pin voltages. VREFHIx can either be driven externally or can be generated by an internal bandgap voltage reference. An external voltage can be supplied to header J15 as an external voltage source for VREFHIx. Note that there is no signal conditioning circuitry in place for an external voltage reference. For best performance, some additional circuitry can be required.