SPRUJH0B April   2025  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 External Power Supply or Accessory Requirements
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Functional Description and Connections
        1. 2.1.1.1 Power Domains
        2. 2.1.1.2 LEDs
        3. 2.1.1.3 Encoder Connectors
        4. 2.1.1.4 Boot Modes
        5. 2.1.1.5 BoosterPack Sites
        6. 2.1.1.6 Analog Voltage Reference
        7. 2.1.1.7 Other Headers and Jumpers
          1. 2.1.1.7.1 USB Isolation Block
          2. 2.1.1.7.2 Alternate Power
          3. 2.1.1.7.3 5V Step-up Converter
        8. 2.1.1.8 Programmable Gain Amplifier (PGA)
      2. 2.1.2 Debug Interface
        1. 2.1.2.1 XDS110 Debug Probe
        2. 2.1.2.2 Virtual COM Port
      3. 2.1.3 Alternate Routing
        1. 2.1.3.1 Overview
        2. 2.1.3.2 GPIO35/GPIO37 Routing
        3. 2.1.3.3 eQEP Routing
        4. 2.1.3.4 X1, X2 Routing
        5. 2.1.3.5 PWM DAC
    2. 2.2 Using the F28E12x LaunchPad
    3. 2.3 BoosterPacks
    4. 2.4 Hardware Revisions
      1. 2.4.1 Revision A
      2. 2.4.2 Revision E2
  9. 3Software
    1. 3.1 Software Development
      1. 3.1.1 Software Tools and Packages
      2. 3.1.2 F28E12x LaunchPad Demo Program
      3. 3.1.3 Programming and Running Other Software on the F28E12x LaunchPad
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 LAUNCHXL-F28E12X Board Dimensions
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Frequently Asked Questions
    2. 5.2 Trademarks
  12. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  13. 7Revision History

2.1.3.2 GPIO35/GPIO37 Routing

To allow for more flexibility when evaluating the F28E12x MCU, this LaunchPad features multiple configurations for routing the GPIO35 and GPIO37 pins. By default, GPIO35 (RXD) and GPIO37 (TXD) are routed to the virtual COM port and are not available on the BoosterPack connector. These GPIO pins support both the SCIA peripheral and the high-speed UARTA peripheral. Alternatively, GPIO35 (TDI) and GPIO37 (TDO) can be routed as JTAG signals to the XDS110 debugger to enable debugging with 4-pin JTAG. When UART or 4-pin JTAG are not needed, the GPIOs can be routed to the BoosterPack connectors for BoosterPack standard functions.

The routing destination of these signal pairs are selected using the on-board switch S2, as described in Table 2-8.

Table 2-8 GPIO35/GPIO37 Select Table - S2
SEL1 (Left)SEL2 (Right)

GPIO35 Function

GPIO37

Function

Intended Use Case

00UART

RXD

UART

TXD

2-pin cJTAG + serial UART

01JTAG

TDI

JTAG

TDO

4-pin JTAG

1

x

BP Header J1.3BP Header J1.4

BoosterPack function

Note that using 4-pin JTAG with serial UART communication to the virtual COM port is not supported on LAUNCHXL-F28E12X hardware. If UART communication is needed, use the 2-pin cJTAG + serial UART configuration.