SPRZ272N September   2007  – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

 

  1. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
    4. 2.4 Silicon Change Overview
  3. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Watchdog: Watchdog Issues Reset After Bad Key is Written
      4. 3.1.4 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without First Verifying if the XRDY Bit is in its Ready State (1)
      5. 3.1.5 Maximum Flash Program Time and Erase Time in Revision O of the TMS320F2833x, TMS320F2823x Real-Time Microcontrollers Data Sheet
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
  4. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  5. 5Documentation Support
  6. 6Trademarks
  7. 7Revision History

2.4 Silicon Change Overview

Table 2-2 lists the change(s) made to each silicon revision.

Table 2-2 TMS320F2833x and TMS320F2823x Silicon Change Overview
REVISIONCHANGES MADE
0First silicon release
AChanges
The following changes are implemented with Revision A:
  • Flash API version 2.00 is needed for Rev A silicon. This version is backward-compatible with Rev 0 silicon.
  • McBSP boot loader

    McBSP loader will now echo back the data received. This was not the case on Rev 0.

  • DMA connection to ePWM

    The ePWM/HRPWM modules can be re-mapped to peripheral frame 3 where they can be accessed by the DMA module.

    In addition, the SOCA and SOCB of each EPWM module is connected to the DMA at the following peripheral interrupt select positions in each channel MODE register (MODE[PERINTSEL(4:0)] bits):

EPWM1-SOCA → PERINTSEL(18)
EPWM1-SOCB → PERINTSEL(19)
EPWM2-SOCA → PERINTSEL(20)
EPWM2-SOCB → PERINTSEL(21)
EPWM3-SOCA → PERINTSEL(22)
EPWM3-SOCB → PERINTSEL(23)
EPWM4-SOCA → PERINTSEL(24)
EPWM4-SOCB → PERINTSEL(25)
EPWM5-SOCA → PERINTSEL(26)
EPWM5-SOCB → PERINTSEL(27)
EPWM6-SOCA → PERINTSEL(28)
EPWM6-SOCB → PERINTSEL(29)

Advisories Fixed

The following advisories are fixed in rev A :

  • Boot to XINTF x16, x32 and Parallel Boot Setup Issue
  • M1 memory access conflict
  • XINTF rogue write for back-to-back accesses to x16/x32 zones.

    Behavior changed such that external delay logic is no longer required to avoid this issue on Rev A. The behavior of the XA0/ XWE1 signal has been modified such that it goes high during inactive cycles. Use the XBANK feature to force inactive cycles between back-to-back zone accesses. See the External Interface (XINTF) chapter of the TMS320x2833x, TMS320x2823x Real-Time Microcontrollers Technical Reference Manual for more information.