SPRZ342O January   2011  – April 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

 

  1.   Abstract
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 CAN Bootloader: Internal Oscillator Tolerance is Not Sufficient for CAN Operation at High Temperatures
      3. 3.1.3 FPU32 and VCU Back-to-Back Memory Accesses
      4. 3.1.4 Caution While Using Nested Interrupts
      5. 3.1.5 Flash: MAX "Program Time” and “Erase Time” in Revision G of the TMS320F2806x Piccolo™ Microcontrollers Data Manual are only Applicable for Devices Manufactured After January 2018
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
  5. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
  6. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

DMA: ePWM Interrupt Trigger Source Selection via PERINTSEL is Incorrect

Revision(s) Affected

0, A, B

Details

The MODE.CHx[PERINTSEL] field bit values of 18–29 should select ePWM1SOCA–ePWM6SOCB as DMA trigger sources. Instead, PERINTSEL values of 18–29 select ePWM2SOCA–ePWM7SOCB as DMA trigger sources as shown below in Table 3-1. ePWM1SOCA and ePWM1SOCB are not implemented as PERINTSEL trigger sources.

Workaround(s)

None

Table 3-1 PERINTSEL Field of Mode Register (MODE)
BITFIELDVALUEDESCRIPTION
4-0PERINTSELPeripheral Interrupt Source Select Bits: These bits select which interrupt triggers a DMA burst for the given channel. Only one interrupt source can be selected. A DMA burst can also be forced via the PERINTFRC bit.
VALUEINTERRUPTSYNCPERIPHERAL
0NoneNoneNo peripheral connection
1ADCINT1NoneADC
2ADCINT2None
3XINT1NoneExternal Interrupts
4XINT2None
5XINT3None
6ReservedNoneNo peripheral connection
7USB0EP1RXNoneUSB-0 End Points
8USB0EP1TXNone
9USB0EP2RXNone
10USB0EP2TXNone
11TINT0NoneCPU Timers
12TINT1None
13TINT2None
14MXEVTAMXSYNCAMcBSP-A
15MREVTAMRSYNCA
16ReservedNoneNo peripheral connection
17ReservedNone
18ePWM2SOCANoneePWM2
19ePWM2SOCBNone
20ePWM3SOCANoneePWM3
21ePWM3SOCBNone
22ePWM4SOCANoneePWM4
23ePWM4SOCBNone
24ePWM5SOCANoneePWM5
25ePWM5SOCBNone
26ePWM6SOCANoneePWM6
27ePWM6SOCBNone
28ePWM7SOCANoneePWM7
29ePWM7SOCBNone
30USB0EP3RXNoneUSB-0 End Points
31USB0EP3TXNone