SPRZ362F November   2012  – October 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28053 , TMS320F28054 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F28055

 

  1. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  3. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 3.1.2 CAN Bootloader: Internal Oscillator Tolerance is Not Sufficient for CAN Operation at High Temperatures
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
  4. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
  5. 5Documentation Support
  6. 6Trademarks
  7. 7Revision History

Advisory

Memory: Prefetching Beyond Valid Memory

Revision(s) Affected

0, A

Details

The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the prefetch occurs past the end of valid memory, then the CPU may receive an invalid opcode.

Workaround

The prefetch queue is 8 x16 words in depth. Therefore, code should not come within 8 words of the end of valid memory. This restriction applies to all memory regions and all memory types (flash, OTP, SARAM) on the device. Prefetching across the boundary between two valid memory blocks is all right.

Example 1: M1 ends at address 0x7FF and is not followed by another memory block. Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8-0x7FF should not be used for code.

Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can be stored up to and including address 0x3FF. Code can also cross into M1 up to and including address 0x7F7.