SPRZ408D June   2014  – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Device and Development Support Tool Nomenclature
    2. 1.2 Revision Identification
  3. 2All Errata Listed With Silicon Revision Number
  4. 3Usage Notes and Known Design Exceptions to Functional Specifications
    1. 3.1 Usage Notes
      1. 3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval
      2. 3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode
    2. 3.2 Known Design Exceptions to Functional Specifications
      1. 3.2.1 Advisory List
      2.      Advisory 1
      3.      Advisory 2
      4.      Advisory 3
      5.      Advisory 4
      6.      Advisory 5
      7.      Advisory 6
      8.      Advisory 7
      9.      Advisory 8
      10.      Advisory 9
      11.      Advisory 10
      12.      Advisory 11
      13.      Advisory 12
      14.      Advisory 13
      15.      Advisory 14
      16.      Advisory 15
      17.      Advisory 16
      18.      Advisory 17
      19.      Advisory 19
      20.      Advisory 20
      21.      Advisory 21
      22.      Advisory 22
      23.      Advisory 24
      24.      Advisory 25
      25.      Advisory 26
      26.      Advisory 27
      27.      Advisory 28
      28.      i2223
      29.      i2224
      30.      i912
      31.      i2225
      32.      i2226
  5. 4Revision History

3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode

DDR3/DDR3L SDRAM specification (JESD79-J3, July 2010) states that "RESET# is recommended to be maintained below 0.2x VDDS_DDR" during initial power ramp. The main reason for this is to ensure the DDR3/DDR3L outputs are in High-Z to avoid an excessive current depending on bus activity. When implementing RTC+DDR mode, an external pull-up resistor of 1K or lower is required on DDR_RESETn to maintain DDR3/DDR3L memory in self-refresh. The external pull-up creates a spec violation during power up because DDR_RESETn will ramp during initial power cycle (the ramp will follow the voltage rail of the pull-up resistor). However, all DDR3/DDR3L I/Os of the AM437x DDR3/DDR3L interface are disabled during power ramp and until DDR3/DDR3L is initialized. Thus, there will be no signal contention and no excessive current on the DDR3/DDR3L interface. This specification violation will not negatively affect the AM437x device or the DDR3/DDR3L memory devices. Note, this violation is only applicable for low-power designs implementing RTC+DDR mode.