SPRZ439I January   2017  – August 2026 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   TMS320F28004x Real-Time MCUs Silicon Errata (Silicon Revisions D, B, A, 0)
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision D Usage Notes and Advisories
    1. 3.1 Silicon Revision D Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 FPU32 and VCU Back-to-Back Memory Accesses
      3. 3.1.3 Caution While Using Nested Interrupts
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision D Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18. 3.2.1 Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24. 3.2.2 Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30. 3.2.3 Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34. 3.2.4 Advisory
      35.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
  7. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
  8. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  9. 7Documentation Support
  10. 8Trademarks
  11. 9Revision History

Advisory

XTAL: XTALCR[SWH]=0 is not supported

Revisions Affected

All

Details

Early versions of the Technical Reference Manual documented XTALCR[2] as 'SWH' with valid settings as either 0 (2 to 10MHz range) or 1 (10 to 20MHz range). This bit field was marked Reserved in subsequent releases and should not be modified by the application.

The datasheet XTAL valid electrical frequency range of 10 to 20MHz remains unchanged since the device initial release.

In device revision 0, A, and B the XTAL will operate with either XTALCR[2] (SWH) setting but may have longer startup times if set to 0.

In device revision D the XTAL will not function if XTALCR[2] (SWH) is set to 0

Workarounds

Keep XTALCR[2] at the hardware default setting of 1.