SPRZ491D december   2020  – june 2023 DRA821U , DRA821U-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0, 2.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0, 2.0 Usage Notes
    2. 3.2 Silicon Revision 1.0, 2.0 Advisories
    3.     i2049
    4.     i2062
    5.     i2091
    6.     i2116
    7.     i2123
    8. 3.3 i2126
    9. 3.4 i2127
    10.     i2134
    11.     i2137
    12.     i2146
    13. 3.5 i2151
    14.     i2157
    15.     i2159
    16.     i2160
    17.     i2161
    18.     i2163
    19.     i2166
    20.     i2177
    21.     i2182
    22.     i2183
    23.     i2184
    24.     i2185
    25.     i2186
    26.     i2187
    27.     i2189
    28.     i2196
    29.     i2197
    30.     i2201
    31.     i2205
    32.     i2207
    33.     i2208
    34.     i2209
    35.     i2216
    36.     i2217
    37.     i2221
    38.     i2222
    39.     i2227
    40.     i2228
    41.     i2232
    42.     i2234
    43.     i2235
    44.     i2237
    45.     i2241
    46.     i2242
    47.     i2243
    48.     i2244
    49.     i2245
    50.     i2246
    51.     i2249
    52.     i2253
    53.     i2257
    54.     i2274
    55.     i2275
    56.     i2277
    57.     i2278
    58.     i2279
    59.     i2283
    60.     i2306
    61.     i2307
    62.     i2310
    63.     i2311
    64.     i2312
    65.     i2320
    66.     i2326
    67.     i2329
    68.     i2351
    69.     i2360
    70.     i2361
    71.     i2362
    72.     i2366
    73.     i2371
    74.     i2372
    75.     i2383
  5.   Trademarks
  6.   Revision History

i2049


ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts

Details:

The ECC Aggregator module is used to aggregate safety error occurrences (which are rare) and generate interrupts to notify software. The ECC Aggregator provides software control over the enabling/disabling and clearing of safety errors interrupts.

When software is performing a clockstop/reset sequence on an IP, the sequence can potentially not complete because the IP's associated ECC Aggregator instance is not idle. The ECC Aggregator idle status is dependent upon any pending safety error interrupts either enabled or disabled, which have not been cleared by software. As a result, the IP's clockstop/reset sequence may never complete (hang) if there are any pending safety errors interrupts that remain uncleared.

Workaround(s):

General Note:

Clockstopping the ECC Aggregator is not supported in functional safety use-cases.

Software should use the following workaround for non-functional safety use-cases:

  1. Enable all ECC Aggregator interrupts for the IP
  2. Service and clear all Pending interrupts
  3. Step 3:
    1. Disable all interrupt sources to the ECC Aggregator, followed by performing Clockstop/reset sequence.
    2. Perform Clockstop/reset sequence, while continuing to service/clear pending interrupts.

Due to interrupts being external stimuli, software has two options for step 3:

  1. Disable all interrupt sources (EDC CTRL checkers) that can generate pending ECC_AGGR interrupts prior to performing the clockstop/reset sequence
  2. Continue to service/clear pending interrupts that occur while performing the clkstop/reset sequence. The sequence would proceed when all interrupts are cleared.

Software in general may need to detect pending interrupts that continuously fire during this entire sequence (ex. in the case of a stuck-at fault scenario), and disable their associated EDC CTRL safety checkers to allow the clockstop/reset sequence to progress towards completion.