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DRA821U-Q1

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Automotive gateway SoC with dual Arm® Cortex®-A72, quad Cortex-R5F, four-port Ethernet switch, PCIe

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DRA821U-Q1

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Product details

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC of 1 Dual Arm Cortex-R5 CPU 64-bit Protocols Ethernet, TSN Ethernet MAC 4-Port 2.5Gb switch PCIe 1 PCIe Gen 3 Features Networking Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC of 1 Dual Arm Cortex-R5 CPU 64-bit Protocols Ethernet, TSN Ethernet MAC 4-Port 2.5Gb switch PCIe 1 PCIe Gen 3 Features Networking Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALM) 433 295.84 mm² 17.2 x 17.2

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4) .

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4) .
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Technical documentation

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* Data sheet DRA821 Jacinto™ Processors datasheet (Rev. D) PDF | HTML 16 Dec 2022
* Errata J7200 DRA821 Silicon Errata (Rev. C) PDF | HTML 27 Jul 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

J7200XSOMXEVM — DRA821 system-on-module

The J7200XSOMG01EVM system-on-module—when paired with the J721EXCP01EVM common processor board—lets you evaluate the DRA821 processor for networking applications throughout automotive and industrial markets. These processors perform particularly well in industrial and automotive gateway (...)

User guide: PDF | HTML
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Evaluation board

J721EXCPXEVM — Common processor board for Jacinto™ 7 processors

The J721EXCP01EVM common processor board for Jacinto™ 7 processors lets you evaluate vision analytics and networking applications in automotive and industrial markets. The common processor board is compatible with all Jacinto 7 processors system-on-modules (sold separately or as a (...)

User guide: PDF | HTML
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Evaluation board

J7EXPCXEVM — Gateway/Ethernet switch expansion card

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

User guide: PDF | HTML
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Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Software development kit (SDK)

PROCESSOR-SDK-J7200 — Software development kit for DRA821 Jacinto™ processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)
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Firmware

VCTR-3P-AUTOSAR — Vector AUTOSAR, HSM, and networking software components for the automotive industry

Vector is the leading manufacturer of software tools and embedded components for the development of electronic systems and networking from CAN to Automotive Ethernet. Vector has been a partner of automotive manufacturers, suppliers and related industries since 1988, providing software components, (...)
From: Vector Informatik GmbH
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IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Products
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Industrial mmWave radar sensors
IWR1443 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 — Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
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IDE, configuration, compiler or debugger

SAFETI_CQKIT — Safety compiler qualification kit

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE, configuration, compiler or debugger

SYSCONFIG — System configuration tool

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Operating system (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino® real-time operating system (RTOS)

The QNX Neutrino® Realtime Operating System (RTOS) is a full-featured and robust RTOS designed to enable the next-generation of products for automotive, medical, transportation, military and industrial embedded systems. Microkernel design and modular architecture enable customers to create (...)
From: QNX Software Systems
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Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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FCBGA (ALM) 433 View options

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