Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.
Up to four general-purpose Arm Cortex-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm Cortex-A72 core unencumbered for advanced and cloud-based applications.
Jacinto DRA821x processors also introduce the Extended MCU (EMCU) concept as a subset of the Main Domain. EMCU is targeted for ASIL-D/SIL-3 functionality and houses the pulsar R5s and dedicated peripherals for additional safety function processing. The functional block diagram highlights which IP belongs to the EMCU. For more details about the EMCU safety concept and domains, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4) .