Dual Arm Cortex-A72, quad Cortex-R5F, 4-port Ethernet switch, and a PCIe controller


Product details


Arm CPU 2 Arm Cortex-A72 Arm MHz (Max.) 2000 Co-processor(s) MCU Island of 1 Dual Arm Cortex-R5, SoC of 1 Dual Arm Cortex-R5 CPU 64-bit Protocols Ethernet, TSN Ethernet MAC 4-port 2.5Gb Switch PCIe 1 PCIe Gen 3 Features Networking Operating system Linux, RTOS Security Debug security, Secure boot & storage & programming, Cryptographic acceleration, Trusted execution environment, Software IP protection, Device identity, Isolation firewalls Rating Automotive Operating temperature range (C) -40 to 125 open-in-new Find other Arm-based processors


Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC


  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA
  • Device security:

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • High-speed interfaces:

    5× gigabit Ethernet ports
    • Integrated Ethernet TSN/AVB switch supporting up to 4 external ports:
      • One 2.5Gb XFI or SGMII
      • Up to 4 1Gb SGMII
      • Up to 4 RMII (10/100) or RGMII (10/100/1000)
      • One 5Gb QSGMII
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB
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Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm Cortex-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm Cortex-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also introduce the Extended MCU (EMCU) concept as a subset of the Main Domain. EMCU is targeted for ASIL-D/SIL-3 functionality and houses the pulsar R5s and dedicated peripherals for additional safety function processing. The functional block diagram highlights which IP belongs to the EMCU. For more details about the EMCU safety concept and domains, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4) .

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Request samples

Preproduction samples are available (XDRA821UXXGALM). Request now

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Technical documentation

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Type Title Date
* Data sheet DRA821 Jacinto™ Processors datasheet (Rev. B) Jan. 31, 2021
* Errata J7200 DRA821 Silicon Errata Dec. 18, 2020
Application note TISCI Server Integration in Vector AUTOSAR Jul. 16, 2021
Application note TDA4 Flashing Techniques Jul. 08, 2021
Application note J721E DDR Firewall Example Jul. 01, 2021
User guide J7200 DRA821 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. A) Jan. 04, 2021
White paper Jacinto™ 7 프로세서의 보안 구현 도구 Jan. 04, 2021
White paper Security Enablers on Jacinto™ 7 Processors Jan. 04, 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren Jan. 04, 2021
Technical article Tailor-made gateway processors lay the groundwork for zone architectures Nov. 17, 2020
User guide Powering DRA821 with TPS6594-Q1 and LP8764-Q1 Oct. 30, 2020
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ Oct. 22, 2020
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors Oct. 22, 2020
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 Oct. 22, 2020
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DRA821 system-on-module
document-generic User guide

The J7200XSOMG01EVM system-on-module—when paired with the J721EXCP01EVM common processor board—lets you evaluate the DRA821 processor for networking applications throughout automotive and industrial markets. These processors perform particularly well in industrial and automotive gateway (...)

  • DRA821 (J7200) processor
  • Mates with the Common Processor board (SOM and CP are needed for base EVM functionality)
  • Optimized power solution (PMIC)
  • DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
  • xSPI NOR flash, 512Mb memory (8bit)
  • HyperFlash + HyperRAM, 512Mb flash memory + 256Mb RAM
document-generic User guide

The J721EXCP01EVM common processor board for Jacinto™ 7 processors lets you evaluate vision analytics and networking applications in automotive and industrial markets. The common processor board is compatible with all Jacinto 7 processors system-on-modules (sold separately or as a (...)

  • UFS flash memory, 32GByte, 2Lane, Gear3
  • USB3.1 type C interface, support DFP, DRP, UFP modes
  • Display port, up to 4K resolution with MST support
  • 2x PCIe card slot, 1x PCIe M.2 slot (M‐Key), all Gen3
document-generic User guide

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

  • Ethernet
    • 4x 10/100/1000Mbps - RGMII ports (DP83867E)
    • 1x 10/100Mbps - RMII port (DP83822I)
  • 6x CAN interface
  • 6x LIN interface
  • PROFI BUS/RS485 port (DB9)
  • USS/IMU sensor header
  • Motor control header
  • Booster pack interface header
  • Board ID EEPROM

Software development

Software Development Kit for DRA821 Jacinto™ processors
PROCESSOR-SDK-J7200 Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)
  • Detailed feature lists for each SDK can be found in the respective release notes links found on the SDK download pages
Code Composer Studio™ integrated development environment (IDE)
CCSTUDIO — Code Composer Studio؜™ software is an integrated development environment (IDE) that supports TI's microcontroller (MCU) and embedded processor portfolios. Code Composer Studio software comprises a suite of tools used to develop and debug embedded applications. The software includes an (...)
Provided by Green Hills Software — The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)

Design tools & simulation

SPRM774.ZIP (185 KB) - Thermal Model
SPRM775.ZIP (2294 KB) - IBIS Model
SPRM776.ZIP (10 KB) - BSDL Model
Pin mux tool
PINMUXTOOL The PinMux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or (...)
Arm-based MPU, arm-based MCU and DSP third-party search tool
PROCESSORS-3P-SEARCH TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
  • Supports many TI processors including Sitara and Jacinto processors and DSPs
  • Search by type of product, TI devices supported, or country
  • Links and contacts for quick engagement
  • Third-party companies located around the world

Reference designs

Gateway automotive reference design
TIDEP-01022 Automotive trends are rapidly evolving, and as a result, new domain- and zonal-based gateway architectures are being used to efficiently handle the ever-increasing amount of data coming into and moving throughout the vehicle, and getting sent to the cloud. A properly functioning domain (or zonal (...)
document-generic Schematic

CAD/CAE symbols

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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