SPRZ570C November   2023  – July 2025 AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
  4. 2Silicon Revision 1.0 Usage Notes and Advisories
    1. 2.1 Silicon Revision 1.0 Usage Notes
      1.      i2324
      2.      i2488
    2. 2.2 Silicon Revision 1.0 Advisories
      1.      i2189
      2.      i2310
      3.      i2374
      4.      i2311
      5.      i2345
      6.      i2351
      7.      i2352
      8.      i2353
      9.      i2354
      10.      i2356
      11.      i2357
      12.      i2358
      13.      i2359
      14.      i2383
      15.      i2392
      16.      i2393
      17.      i2394
      18.      i2401
      19.      i2404
      20.      i2405
      21.      i2426
      22.      i2427
      23.      i2428
      24.      i2433
      25.      i2438
      26.      i2439
      27.      i2485
      28.      i2486
  5. 3Trademarks
  6. 4Revision History

i2488


CLOCKS : PLL Cofiguration for presice 50-50 Duty cycle clocks

Details:

The VCO within a PLL can generate output waveforms with varying duty cycles, which can not meet the requirement for a precise 50-50 duty cycle needed by system & peripherals.

Severity:

Minor

Workaround(s):

Configure the PLL to operate at twice (2x) the target frequency. Configure the clock divider (HSDIVIDER) register to divide the PLL output by 2.