SPVA062 June 2026 PCM4220 , PCM4222 , TLV320ADC6120 , TLV320ADC6140
Figure 2-1 presents simple first-order Δ-Σ modulator with a one-bit output. The output of the integrator is digitized through a comparator (or a one-bit ADC). This output is fed back to the input signal through a one-bit DAC. This error signal is the input to the integrator.
This conversion is done at a rate much higher than the overall sampling rate of the ADC itself. This helps with:
At near-idle inputs (0V), the output of the comparator stage has a repeating pattern of 0101…, which translates to a spike at , Fmod being the sampling frequency of the modulator. With non-idealities like
The spike frequencies change to , the Δf is the frequency change brought about by these non-idealities. These spikes, when decimated to an output sampling rate of Fs, can result in the "idle tones" being observed in the audible band of the ADC.
While the integrated noise can still be low and within spec, having tones above the actual noise floor is still an undesirable artifact in applications where the output is amplified before post-processing or passed to a speaker amplifier. While modern day audio ADCs are designed with multi-bit Δ-Σ modulators to obtain improved noise performance, repeating patterns with idle inputs still result in tones in the audio spectrum.
However, these repeating patterns are not there when the input is a moving signal. Figure 2-2 shows the FFT spectrum on the TLV320ADC6120 ADC (a) when the inputs are idle, and (b) with a -60dBFS, 1kHz sinusoidal signal. Figure 2-3 shows the FFT spectrums under the same input conditions on the PCM4222 ADC.
As is clearly visible in both Figure 2-2 and Figure 2-3, these tones disappear with input signals moving at amplitudes as low as -60dBFS.