SWAU130A March   2023  – December 2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Hardware Features
    2. 2.2 Connector and Jumper Descriptions
      1. 2.2.1 LED Indicators
      2. 2.2.2 Jumper Settings
      3. 2.2.3 BoosterPack Header Assignment
      4. 2.2.4 JTAG Headers
    3. 2.3 Power
      1. 2.3.1 Measure the CC3301 Current Draw
        1. 2.3.1.1 Low Current Measurement (LPDS)
        2. 2.3.1.2 Active Current Measurement
    4. 2.4 Clocking
    5. 2.5 Performing Conducted Testing
  7. 3Implementation Results
    1. 3.1 Evaluation Setups
      1. 3.1.1 MCU and RTOS
      2. 3.1.2 Processor and Linux
      3. 3.1.3 Standalone RF Testing
        1. 3.1.3.1 Radio Tool BP-CC3301 Hardware Setup
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

2.2.3 BoosterPack Header Assignment

The CC3301 BoosterPack has 2 x 20 pin connectors that provide access to many of the CC3301 pins and features. The signal assignment on these 2x20 pin connectors is shown in the figure below and described in Table 3-3 and Table 3-4.

GUID-20231208-SS0I-B7W6-JV41-XNMDT2G32SXH-low.svg Figure 2-3 BP-CC3301 BoosterPack Header Pinout
Table 2-3 P1 Header Pin Assignment
Pin Name (in schematic) Type/ Direction Description
P1.1 VCC_MCU_3V3 Input No functional purpose.
P1.2 Reserved N/A N/A
P1.3 UART_TX_3V3 (from CC3301) Output The CC3301 UART TX to host for BLE host controller interface.
P1.4 UART_RX_3V3 (to CC3301) Input The CC3301 UART RX from host for BLE host controller interface.
P1.5 LP_RESET Input Reset line for CC3301 used to enable/ disable (active low). Driven by host through LaunchPad pins.
P1.6 Reserved N/A N/A
P1.7 SDIO_CLK_3V3 Input SDIO clock or SPI clock. Must be driven by host.
P1.8 IRQ_WL_3V3 Output Interrupt request from CC3301 to host for Wi-Fi activity.
P1.9 COEX_GRANT_3V3 Output External coexistence interface - grant (reserved for future use).
P1.10 ANT_SEL_3V3 Output Antenna select control.
P1.21 VCC_MCU_5V Power 5 V supply to board.
P1.22 GND GND Board ground
P1.23 Reserved N/A N/A
P1.24 Reserved N/A N/A
P1.25 Reserved N/A N/A
P1.26 Reserved N/A N/A
P1.27 Reserved N/A N/A
P1.28 Reserved N/A N/A
P1.29 COEX_REQ_3V3 Input External coexistence interface - request (reserved for future use).
P1.30 COEX_PRIORITY_3V3 Input External coexistence interface - priority (reserved for future use).
Table 2-4 P2 Header Pin Assignment
Pin Name (in schematic) Type/Direction Description
P2.11 IRQ_BLE_3V3 Output Interrupt request from CC3301 to host for BLE activity.
P2.12 Reserved N/A N/A
P2.13 Reserved N/A N/A
P2.14 SDIO_D0_3V3 (POCI) Input/Output SDIO data D0 or SPI POCI.
P2.15 SDIO_CMD_3V3 (PICO) Input/Output SDIO command or SPI PICO.
P2.16 Reserved N/A N/A
P2.17 FAST_CLK_REQ_3V3 Output Fast clock request from CC3301 to host.
P2.18 SDIO_D3_3V3 (CS) Input/Output SDIO data D3 or SPI CS.
P2.19 SLOW_CLK_IN_3V3 Input Input for external RTC clock 32.768 kHz.
P2.20 GND GND Board ground
P2.31 Reserved N/A N/A
P2.32 Reserved N/A N/A
P2.33 Reserved N/A N/A
P2.34 LOGGER_3V3 Output Tracer from CC3301 (UART TX debug logger).
P2.35 Reserved N/A N/A
P2.36 UART_RTS_3V3 (from CC3301) Output UART RTS from CC3301 to host for BLE HCI flow control.
P2.37 UART_CTS_3V3 (to CC3301) Input UART CTS to CC3301 from host for BLE HCI flow control.
P2.38 SDIO_D1_3V3 Input/Output SDIO data D1.
P2.39 SDIO_D2_3V3 Input/Output SDIO data D2.
P2.40 Reserved N/A N/A