SWRS202C May   2017  – January 2022 AWR1443

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements (1)
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

9.4.2 Main (Control) System

The Main (Control) System includes ARM’s automotive grade Cortex-R4F processor clocked at 200 MHz, which is user programmable. User applications executing on this processor control the overall operation of the device, including Radar Control via well-defined API messages, radar signal processing (assisted by the radar hardware accelerator) and peripherals for external interface.

The Main (Control) System plays a big role in enabling autonomous operation of AWR1443 as a radar-on-a-chip sensor. The device includes a quad serial peripheral interface (QSPI) which can be used to download customer code directly from a serial flash. A (classic) CAN interface is included that can be used to communicate directly from the device to a CAN bus. An SPI/I2C interface is available for power management IC (PMIC) control when the AWR1443 is used as an autonomous sensor.

For more complex applications, the device can operate under the control of an external MCU, which can communicate with AWR1443 device over an SPI interface. In this case, it is possible to use the AWR14xx as a radar sensor, providing raw detected objects to the external MCU. External MCU could reduce the application code complexity residing in the device and makes more memory available for radar data cube inside the AWR1443. This configuration also eliminates the need for a separate serial flash to be connected to the AWR1443.

Furthermore, the external MCU can provide faster interfaces, such as CAN-FD or Ethernet, for the radar sensor to connect to a central processing unit (CPU). In such a distributed configuration, multiple AWR1443 devices mounted around the vehicle can connect to the CPU, providing a surround view. The external MCU itself is low-cost, because the low-level radar signal processing is accomplished inside the AWR1443, using the hardware accelerator, while the higher-layer intelligence and complex algorithms reside in the common CPU, making the overall solution cost-effective.

Note that although four interfaces – one CAN, one I2C and two SPI interfaces – are present in the AWR1443 device for external communication and PMIC control, only two of these interfaces are usable at any point in time.

The total memory (RAM) available in the Main subsystem is 576 KB. This is partitioned between the R4F program RAM, R4F data RAM and radar data memory. The maximum usable size for R4F is 448 KB and this is partitioned between the R4F’s tightly coupled interfaces TCMA (320 KB) and TCMB (128 KB). Although the complete 448 KB is unified memory and can be used for program or data, typical applications use TCMA as program and TCMB as data memory.

The remaining memory, starting at a minimum of 128 KB, is available to be used as radar data memory for storing the ‘radar data cube’. It is possible to increase the radar data memory size in 64 KB increments, at the cost of corresponding reduction in R4F program or data RAM size. The maximum size of radar data memory possible is 384 KB. A few example configurations supported are listed in #GUID-0A28B289-8932-43E0-8103-1C305498357E/T4362547-31.

Table 9-1 R4F RAM(1)
OPTIONR4F PROGRAM RAMR4F DATA RAMRADAR DATA MEMORY
1320KB128KB128KB
2256KB128KB192KB
3256KB64KB256KB
4128KB64KB384KB
(1) For AWR1443 ES version 1.0, available RAM is 448 KB instead of 576KB.

The Main Subsystem, Cortex-R4F memory map is shown in #GUID-0A28B289-8932-43E0-8103-1C305498357E/T4362547-33.

Table 9-2 Main System Memory Map
NameFrame Address (Hex)SizeDescription
StartEnd
CPU Tightly Coupled Memories
TCMA ROM0x0000_00000x0001_FFFF96KiBProgram ROM
TCM RAM-A0x0020_00000x0024_FFFF128–320KiBMemory size is dependant on the allocation done in #GUID-0A28B289-8932-43E0-8103-1C305498357E/T4362547-31, R4F RAM
TCM RAM-B0x0800_00000x0802_FFFF64–128KiB
System Peripherals
Mail Box
MSS<->RADARSS		0xF060_10000xF060_17FF2KiBRADARSS to MSS mailbox memory space
0xF060_20000xF060_27FF2KiBMSS to RADARSS mailbox memory space
0xF060_80000xF060_80FF188BMSS to RADARSS mailbox Configuration Registers
0xF060_80600xF060_86FF188BRADARSS to MSS mailbox Configuration Registers
PRCM & Control Module0xFFFF_E1000xFFFF_E2FF756BTOP Level Reset, Clock management registers
0xFFFF_FF000xFFFF_FFFF256BMSS Reset, Clock management registers
0xFFFF_EA000xFFFF_EBFF512KiBIO Mux module registers
0xFFFF_F8000xFFFF_FBFF352BGeneral-purpose control registers
0x5000_0400584BTPCC,TPTC,ADC buffer configuration, status registers
GIO0xFFF7_BC000xFFF7_BDFF180BGIO module configuration registers
DMA0xFFFF_F0000xFFFF_F3FF1KiBDMA-1 module configuration registers
VIM0xFFFF_FD000xFFFF_FEFF512BVIM module configuration registers
RTI-A0xFFFF_FC000xFFFF_FCFF192BRTI-A module
RTI-B0xFFFF_EE000xFFFF_EEFF192BRTI-B module register space
Serial Interfaces and Connectivity
QSPI0xC000_00000xC07F_FFFF8MBQSPI –Flash Memory space
0xC080_00000xC0FF_FFFF116BQSPI module configuration registers
MIBSPI0xFFF7_F4000xFFF7_F5FF512BMIBSPI-A module configuration registers
SPI0xFFF7_F6000xFFF7_F7FF512BSPI module configuration registers
SCI-A/UART0xFFF7_E5000xFFF7_E5FF148BSCI-A module configuration registers
SCI-B/UART0xFFF7_E7000xFFF7_E7FF148BSCI-B module configuration registers
CAN0xFFF7_DC000xFFF7_DDFF512BCAN module configuration registers
I2C0xFFF7_D4000xFFF7_D4FF112BI2C module configuration registers
ADC Buffer0x5200_000016KiBADC ping pong buffer memory space
CBUF_FIFO0x5202_000016KiBCommon buffer memory space
Hardware FFT accelerator0x5008_00000x5008_07FF512BFFT Accelerator PARAM memory
0x5008_08000x5008_0FFF264BFFT accelerator Configuration registors
0x5008_10004KiBFFT accelerator Window registers
0x5203_00000x5203_7FFF32KiBFFT accelerator Memory -1 space
0x5203_800032KiBFFT accelerator Memory -2 space
L3 Memory
L3 Shared Memory0x5100_0000384KiBL3 Shared memory space
Interconnects
PCR0xFFF7_80000xFFF7_87FF1KiBPCR-1 interconnect configuration port
PCR-20xFCFF_10000xFCFF_17FF1KiBPCR-2 interconnect configuration port
128 bit SCR0x5207_0000128B128 bit SCR configuration port
Safety Modules
CRC0xFE00_00000xFEFF_FFFF16KiBCRC module configuration registers
PBIST0xFFFF_E4000xFFFF_E5FF464BPBIST module configuration registers
STC0xFFFF_E6000xFFFF_E7FF284BSTC module configuration registers
DCC-A0xFFFF_EC000xFFFF_ECFF44BDCC-A module configuration registers
DCC-B0xFFFF_F4000xFFFF_F4FF44BDCC-B module configuration registers
ESM0xFFFF_F5000xFFFF_F5FF156BESM module configuration registers
CCMR40xFFFF_F6000xFFFF_F6FF136BCCMR4 module configuration registers
Peripheral Memories (System & Non System)
CAN RAM0xFF1E_00000xFF1F_FFFF128KBCAN RAM memory space
DMA RAM0xFFF8_00000xFFF8_0FFF4KBDMA RAM memory space
VIM RAM0xFFF8_20000xFFF8_2FFF2KBVIM RAM memory space
MIBSPIA-TX RAM0xFF0E_00000xFF0E_01FF0.5KBMIBSPIA-TX RAM memory space
MIBSPIA- RX RAM0xFF0E_02000xFF0E_03FF0.5KBMIBSPIA- RX RAM memory space
Debug Modules
Debug Sub System0xFFA0_00000xFFAF_FFFF244KiBDebug subsystem memory space and registers