SWRS283A June   2022  – November 2022 IWR6243

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 LVDS Interface Configuration
        1. 8.9.6.1 LVDS Interface Timings
      7. 8.9.7 General-Purpose Input/Output
        1. 8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.9.8 Camera Serial Interface (CSI2)
        1. 8.9.8.1 CSI2 Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  10. 10Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Radar Sensor for Industrial Applications
    3. 11.3 Imaging Radar using Cascade Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Export Control Notice
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2.     Package Option Addendum
    3. 13.2 Tape and Reel Information
    4.     Tray Information
    5.     Mechanical Data

8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Receiver Noise figure   10   dB
1-dB compression point (Out Of Band)#T4362547-134   –12   dBm
Conversion gain at 48db gain setting   47   dB
Gain range 18 dB
Gain step size   2   dB
IF bandwidth#X3038     20 MHz
ADC sampling rate
(Real/ PseudoReal/ Complex 2x)		     45 Msps
ADC sampling rate
(Complex 1x)		     22.5 Msps
ADC resolution 12 Bits
Idle Channel Spurs –95 dBFS
Transmitter Output power 11.7 dBm
Phase shifter accuracy -11.25 +16.875 °
Power backoff range 26 dB
Clock subsystem Frequency range 57 64 GHz
Ramp rate 250 MHz/µs
Phase noise at 1-MHz offset –93 dBc/Hz
20 GHz SYNC OUT signal (FM_CW_CLKOUT and FM_CW_SYNCOUT) Frequency range 19 21.33 GHz
Output power at the pin 7.5 dBm
Return loss –8 dB

Impedance

50

 Ω
20 GHz SYNC IN signal (FM_CW_SYNCIN) Frequency range 19 21.33 GHz
Input power at the pin -3 3#GUID-E4C1CB6F-C34C-4099-AE7A-087C157B82BE dBm
Return loss –8 dB
Impedance 50 Ω
(1) 1-dB Compression Point (Out Of Band) is measured by feeding a continuous wave tone below the lowest HPF cut-off frequency (10 kHz).
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1HPF2
175,235,350,700350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
  • Less than ±0.5 dB pass-band ripple/droop, and
  • Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
(3) The device can tolerate upto 6dBm at temperatures below 70°C TJ.

#T4362547-148 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

GUID-20210127-CA0I-13FG-JLLX-PFXSSG9TGFW9-low.gifFigure 8-1 Noise Figure, In-band P1dB vs Receiver Gain