SWRS283A June   2022  – November 2022 IWR6243

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 LVDS Interface Configuration
        1. 8.9.6.1 LVDS Interface Timings
      7. 8.9.7 General-Purpose Input/Output
        1. 8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.9.8 Camera Serial Interface (CSI2)
        1. 8.9.8.1 CSI2 Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  10. 10Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Radar Sensor for Industrial Applications
    3. 11.3 Imaging Radar using Cascade Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Export Control Notice
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2.     Package Option Addendum
    3. 13.2 Tape and Reel Information
    4.     Tray Information
    5.     Mechanical Data

6 Device Comparison

Table 6-1 Device Features Comparison
FUNCTION IWR6243(6) IWR6843AOP IWR6843 IWR6443 IWR1843 IWR1642 IWR1443
Antenna on Package (AOP) — Yes — — — — —
Number of receivers 4 4 4 4 4 4 4
Number of transmitters 3(1) 3(1) 3(1) 3(1) 3(1) 2 3
RF frequency range 57 to 64 GHz 60 to 64 GHz 60 to 64 GHz 60 to 64 GHz 76 to 81 GHz 76 to 81 GHz 76 to 81 GHz
On-chip memory — 1.75MB 1.75MB 1.4MB 2MB 1.5MB 576KB
Max I/F (Intermediate Frequency) (MHz) 20 10 10 10 10 5 15
Max real sampling rate (Msps) 45 25 25 25 25 12.5 37.5
Max complex sampling rate (Msps) 22.5 12.5 12.5 12.5 12.5 6.25 18.75
Processors
MCU (R4F) — Yes Yes Yes Yes Yes Yes
DSP (C674x) — Yes Yes — Yes Yes —
Peripherals
Serial Peripheral Interface (SPI) ports 1 2 2 2 2 2 1
Quad Serial Peripheral Interface (QSPI) —(5) Yes Yes Yes Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1 1 1 1 1 1
Controller Area Network (DCAN) interface — — — — Yes Yes Yes
Controller Area Network (CAN-FD) interface — Yes Yes Yes Yes — —
Trace — Yes Yes Yes Yes Yes —
PWM — Yes Yes Yes Yes Yes —
Hardware In Loop (HIL/DMM) — Yes Yes Yes Yes Yes —
GPADC Yes Yes Yes Yes Yes Yes Yes
LVDS/Debug(2) Yes Yes Yes Yes Yes Yes Yes
CSI2 Yes — — — — — Yes
Hardware accelerator — Yes Yes Yes Yes — Yes
1-V bypass mode Yes Yes Yes Yes Yes Yes Yes
Cascade (20-GHz sync) Yes — — — — — —
JTAG —(3) Yes Yes Yes Yes Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD(4) PD(4) PD(4) PD(4) PD(4) PD(4) PD(4)
(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin.
(2) LVDS Interface is not a production Interface and is only used for debug.
(3) JTAG is used for Boundary SCAN purposes.
(4) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.
(5) QSPI interface is only used for development and is not supported in production
(6) Developed for Functional Safety applications, the device supports hardware integrity upto SIL-2. Refer to the related documentation for more details.