SWRS304D October 2024 – November 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1
PRODMIX
| PARAMETERS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fSCLK | SCLK clock input frequency | VDDS = 1.71V | 3.1 | MHz | ||
| fSCLK | SCLK clock input frequency | VDDS = 3.8V | 6.145 | MHz | ||
| SCLKDC | SCLK clock duty cycle | VDDS = 1.71V | 35% | 65% | ||
| SCLKDC | SCLK clock duty cycle | VDDS = 3.8V | 40% | 60% | ||
| tSDOUT,valid | SD data output valid time (Falling edge of SCLK to SD data valid) | 26 | 47 | ns | ||
| tWS,setup | WS data input setup time (before rising edge of SCLK) | 15 | ns | |||
| tWS,hold | WS data input hold time (after rising edge of SCLK) | 0 | ns | |||
| tSDIN,setup | SD data input setup time (before rising edge of SCLK) | 9 | ns | |||
| tSDIN,hold | SD data input hold time (after rising edge of SCLK) | 5 | ns | |||