SWRZ062F September   2015  – December 2022 CC1310

 

  1.   CC1310 SimpleLink™ Ultra-Low-Power Sub-1 GHz Wireless MCU Silicon Revisions B, A
  2.   Trademarks
  3. 1Advisory Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision B Advisories
    1.     Advisory 02
    2.     Advisory 03
    3.     Advisory 04
    4.     Advisory 05
    5.     Advisory 06
    6.     Advisory 07
    7.     Advisory 08
    8.     Advisory 09
    9.     Advisory 10
    10.     Advisory 11
    11.     Advisory 12
    12.     Advisory 13
    13.     Advisory 14
    14.     Advisory 15
    15.     Advisory 16
    16.     Advisory 17
    17.     Advisory 18
    18.     Advisory 19
  6. 4Silicon Revision A Advisories
    1.     Advisory 01
  7. 5Revision History

Advisory 04

Slave Mode Can Sample New TX Data From SYSBUS Clock Domain Using SSPCLK With No Synchronization

Revision Affected:

A and B

Details:

When the SSI is programmed to operate in slave mode, the data written to the SSI data register (SSIn:DR) in the SYSBUS clock domain can be sampled in the SSPCLK domain or without any synchronization. This sampling condition occurs when all of the following conditions are met:

  • The SSI Transmit FIFO is empty.
  • The SSI Data register (SSIn:DR) write access occurs as a new SPI master transfer starts.
  • The SSI slave-state machine samples data to transmit.

This issue causes written data to be lost.