SWRZ097D April   2020  – November 2022 AWR6843

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24. 6.3 ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#15
    28.     ANA#16
    29.     ANA#17A
    30.     ANA#18B
    31.     ANA#19
    32.     ANA#20
    33.     ANA#21
    34.     ANA#22A
    35.     ANA#27A
  7. 7Trademarks
    1.     Revision History

MSS#40

Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC

Revision(s) Affected:

AWR6843 ES2.0

Description:

As per TPTC IP Spec, a Transfer request (TR) is supposed to access a single slave end point. ACCEL_MEM0/ACCEL_MEM1 memory banks of HWA are available via single slave point and ACCEL_MEM2/ ACCEL_MEM3 memory banks of HWA are available as another slave point (different from that of ACCEL_MEM0/ ACCEL_MEM1). Hence if a single TR is used to access a buffer spanning ACCEL_MEM1 and ACCEL_MEM2 memories of the HWA (i.e. a single buffer spanning 2 different slave points), the spec is not being adhered to. This errata is explicitly highlighting this spec requirement

Workaround(s):

TBSplit the access into 2 TRs so that a single TR does not span ACCEL_MEM1 +ACCEL_MEM2. The 2 TRs can be chained.