SWRZ137C December   2022  – December 2025 IWRL6432

PRODUCTION DATA  

  1.   1
  2.   ABSTRACT
  3. 1Introduction
  4. 2Device Nomenclature
  5. 3Device Markings
  6. 4Usage Notes
    1. 4.1 Power up sequence in power optimized topology
    2. 4.2 Meeting data sheet spec for 1.2V Digital LDO output path in BOM optimized topology
  7. 5Advisory to Silicon Variant / Revision Map
  8. 6Known Design Exceptions to Functional Specifications
    1. 6.1  ANA #48
    2. 6.2  ANA #49
    3. 6.3  ANA #50
    4. 6.4  ANA #51
    5. 6.5  ANA #52
    6. 6.6  ANA #57
    7. 6.7  DIG #1
    8. 6.8  DIG #2
    9. 6.9  DIG #3
    10. 6.10 DIG #4
    11. 6.11 DIG #5
    12. 6.12 DIG #6
    13. 6.13 DIG #7
    14. 6.14 DIG #8
    15. 6.15 DIG #9
    16. 6.16 DIG #10
    17. 6.17 DIG #14
    18. 6.18 DIG #15
    19. 6.19 DIG #16
  9. 7Trademarks
  10.   Revision History

6.15 DIG #9

TOP_IO_MUX register space not accessible from RS232 for debug purposes

Revisions Affected

IWRL6432 ES1.0, ES2.0

Details

RS232 is not able to write TOP_IO_MUX registers unless the space is programmed for user mode access.

Workaround

TI recommends to use the following sequence:

  1. From Processor or DAP : Unlock TOP_IO_MUX registers (by programming LPRADAR:TOP_IO_MUX:IOCFGKICK0 = 83E7 0B13h and LPRADAR:TOP_IO_MUX:IOCFGKICK1 = 95A4 F1E0h )
  2. From Processor or DAP : Write to TOP_IO_MUX registers, LPRADAR:TOP_IO_MUX:USERMODEEN should be set to 0xADADADAD
  3. Now TOP_IO_MUX registers can be accessed from RS232.

The below table shows the Register Addresses for above workaround.

Bits

Name

Address

0:31

 LPRADAR:TOP_IO_MUX:IOCFGKICK0

0x5A000068

0:31

 LPRADAR:TOP_IO_MUX:IOCFGKICK 0x5A00006C

0:31

 LPRADAR:TOP_IO_MUX:USERMODEEN 0x5A000060