SWRZ161C December   2024  – August 2026 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Advisories Matrix
  5. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support—Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  6. 3Advisories
    1. 3.1  ADC_08
    2. 3.2  ADC_09
    3. 3.3  BATMON_01
    4. 3.4  BATMON_02
    5. 3.5  SYS_204
    6. 3.6  SYS_206
    7. 3.7  SYS_207
    8. 3.8  SYS_211
    9. 3.9  APU_201
    10. 3.10 HSM_01
    11. 3.11 UDMA_01
    12. 3.12 RADIO_05
    13. 3.13 SYSROM_01
  7. 4Revision History

3.11 UDMA_01

μDMA write response to a peripheral’s single request can be missed.

Revisions Affected

E and F

Details

μDMA responds to single and burst requests from peripherals. In case the write access(es) from μDMA is(are) intercepted by the interconnect write buffers due to arbitration loss, the peripheral can raise a second spurious single or burst request. Since the μDMA responds to the second request after the peripheral’s FIFO gets full with earlier write buffer contents, the second write(s) is(are) ignored by the peripheral and get(s) missed. This issue is seen only during data transfers via μDMA TX channels. This issue is not seen on the μDMA RX channels, since the read path through the interconnect does not include write buffers.

Workaround

μDMA SETBURST is configured to use BURST requests.

μDMA arbitration size is 2.

TX FIFO level trigger is set to ≤ 1/4 empty.

This workaround is to be incorporated into future releases of SimpleLink™ Low Power F3 software development kit (SDK).