TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

3.1.1.2 Input Reference Signals

Use the following options when setting up the input reference signals:

  • Option 1: The onboard reference LMK61E2 (U2) is powered up using the jumper J16 and factory programmed to generate a 156-MHz LVDS output. U2 can be programmed to generate different clock frequencies using the I2C interface. The clocking board has a CDCLVP111-SP clock buffer (U9) to select the reference input from U2 or external reference, Y1, and distribute to the clocking devices on the board. U9 can select the LMK61E2 reference using the short jumper at pin 2-3 of the jumper J30. Isolate the power supply to Y1 by removing the short jumper at J8.
  • Option 2: Connect the external reference signal to the OSCin_P and OSCin_N connectors. While connecting the external reference, power down the Y1 by removing the short jumper at J8 and remove C87. For external reference enable to clocking devices from reference buffer device U13, place the short jumper at pin 1-2 of J30. At the same time, isolate the power supply to U2 by removing the jumper J16.
  • Option 3: The onboard VCXO Y1 is powered on using the jumper J8 and outputs a 100-MHz signal to the CLK0_P pin input of clock buffer (U9) by removing R39 and connect 50 Ω at OSCin_N connector. Place the short jumper at pin 1-2 of J30 and distribute the reference to clocking devices. At the same time, isolate the power supply to U2 by removing the jumper J16.
  • Option 4: Use one of the previous options, when LMK04832-SP works in single PLL mode (PLL2). When LMK04832-SP is operating in distribution mode or dual PLL mode, connect the external reference to J6 or J10 or J5 depending on the operating input frequencies. Next, choose between the LMH5401-SP based active balun (U6) or onboard passive balun (U40). Finally, select the path to CLKin1 pins of the U1 by placing C79 and C80 or C38 and C3. While operating in distribution mode, power down the Y1 by removing jumper J8. In distribution mode, when the input frequency is higher than 3 GHz, then the external clock input through the J5 connector can be fed to Fin0 pins of the LMK04832-SP and connect the external clock through R553 and R554 and remove R555 and R556.