TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

3.2.2 Clocking Board Programming Sequence

TIDA-010191 clocking board includes the FTDI device, which needs to be programmed once to support the software GUI. An FTDI utility FT-prog is installed from the web. The product description is set to TIDA01019x as shown in Figure 3-4.

GUID-20221202-SS0I-1CBM-S4W5-PHLVFZJK5MQW-low.svg Figure 3-4 Screenshot of the FTDI Setup

Clocking board devices are programmed by HSDC TIDA01019x GUI and can be downloaded from the TIDA-010191 tool page.

GUID-20221202-SS0I-06DP-QPVF-BNJ4WTSVNWLX-low.png Figure 3-5 Clock GUI

All devices are configured by loading the configuration files in the low level view page.

  • To measure LMX2615-SP phase noise, configure the following:
    • External reference at 100 MHz provided through Wenzel source
    • The LMX2615-SP devices are taking a reference via CDCLVP111-SP. The LMX2615-SP is programmed for a 100-MHz reference and 200-MHz phase detector frequency at various frequencies to measure the phase noise
  • To measure clock skew, configure the following:
    • The LMK61E2 is programmed at 100 MHz. Configure the file in the low level view page
    • The LMK04832-SP is programmed in single PLL mode with 100-MHz reference and generates 20-MHz SYSREF frequency and provides the SYSREFREQ and SYNC signals to both LMX2615-SP devices
    • Both LMX2615-SP devices are programmed with the common configuration file at a 100-MHz phase detector frequency and generate a 3.2-GHz RFoutA and SYSREF in repeater mode at 20-MHz SYSREFout (RFoutB) from both devices
  • To measure the ADC12DJ3200-SP SNR and skew between multiple ADC EVMs, configure the following:
    • The LMK61E2 is programmed at 100 MHz. Configure the file in the low level view page
      • LMK61E2_100M.cfg
      • LMK61E2_EEPROM_Write.cfg
    • The LMK04832-SP is programmed in single PLL mode with 100-MHz reference and generates 20-MHz SYSREF frequency and provides the SYSREFREQ and SYNC signals to both LMX2615-SP devices. The device also generates the FPGA clocks and FPGA SYSREFs for TSW14J57 capture cards
      • Load LMK04832-SP_160MFCLK_20MSYSREF_100MREF.cfg
    • Both LMX2615-SP devices are programmed with the common configuration file at a 100-MHz phase detector frequency and generate a 3.2-GHz RFoutA and SYSREF in repeater mode at 20-MHz SYSREFout (RFoutB) from both devices
      • LMX2615-SP_AB_3.2G_100MREF_SYSREF_Repeater.cfg