TIDUEZ8C december   2022  – june 2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Insulation Monitoring
    2. 1.2 Impact of Parasitic Isolation Capacitance
    3. 1.3 IEC 61557-8 Standard for Industrial Low-Voltage Distribution Systems
    4. 1.4 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TPSI2140
      2. 2.2.2 AMC3330
      3. 2.2.3 TPS7A24
      4. 2.2.4 REF2033
      5. 2.2.5 TLV6001
    3. 2.3 Design Considerations
      1. 2.3.1 Resistive Bridge
      2. 2.3.2 Isolated Analog Signal Chain
        1. 2.3.2.1 Differential to Single-Ended Conversion
        2. 2.3.2.2 High-Voltage Measurement
        3. 2.3.2.3 Signal Chain Error Analysis
      3. 2.3.3 Loss of PE Detection
      4. 2.3.4 Insulation Monitoring on AC Lines
      5. 2.3.5 PCB Layout Recommendations
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Connectors
      2. 3.1.2 Default Jumper Configuration
      3. 3.1.3 Prerequisites
    2. 3.2 Software Requirements
    3. 3.3 Software
    4. 3.4 Test Setup
    5. 3.5 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  11. 5About the Author
  12. 6Revision History

3.3 Software

Table 3-3 details the software flow.

Table 3-3 Software flow and timing
STEP TIME (μs) COMMENT
Board initialization 2929 One time after power up
Close SP + ADC Voltage settling 500 Time to close the switch SP and delay of 500 μs for the voltage at the ADC input to settle. Depending on capacitive loading this time needs to be adjusted (see Section 1.2).
Measure Viso,P and VDC,P 126 Both voltages are measured 20 times interleaved and averaged, to minimize noise
Open SP and close SN 400 A delay of 400 μs is implemented between the opening SP and closing SN.
ADC Voltage settling 500 Delay of 500 μs for the voltage at the ADC input to settle. Depending on capacitive loading this time needs to be adjusted (see Section 1.2).
Measure Viso,N and VDC,N 126 Both voltages are measured 20 times interleaved and averaged, to minimize noise
Calculate Riso,P and Riso,N 13 Final calculation of Riso,P and Riso,N

The software initialization takes about 3 ms and must be completed once after power up. Each measurement of the insulation resistances afterward takes 1.7 ms. This fast measurement time is one of the big advantages of using the TPSI2140 compared to a traditional relay for switching in the measurement path. The switching behavior of the TPIS2140 and voltage settling at the ADC input is shown in Figure 3-1.

GUID-20220929-SS0I-MGH3-03LV-LZTND0LNKTK2-low.png
Blue: Enable Signal, Green: Voltage across TPSI2140, Yellow: Voltage at ADC input
Figure 3-1 Switching Behavior of TPSI2140 and ADC Input Voltage