TIDUF03 December   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 System Design Theory
      1. 2.2.1 Detection Principals
      2. 2.2.2 Saturation
      3. 2.2.3 General Mode of Operation
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8220
      2. 2.3.2 OPAx202
      3. 2.3.3 TLVx172
      4. 2.3.4 TLV7011
      5. 2.3.5 INA293
      6. 2.3.6 SN74LVC1G74
      7. 2.3.7 TLV767
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1  Board Overview
      2. 3.1.2  Filter Stage
      3. 3.1.3  Differential to Single-Ended Converter
      4. 3.1.4  Low-Pass Filter
      5. 3.1.5  Full-Wave Rectifier
      6. 3.1.6  DC Offset Circuit
      7. 3.1.7  Auto-Oscillation Circuit
        1.       31
      8. 3.1.8  DRV8220 H-Bridge
      9. 3.1.9  Saturation Detection Circuit
      10. 3.1.10 H-Bridge Controlled by DFF
      11. 3.1.11 MCU Selection
      12. 3.1.12 Move Away From Timer Capture
      13. 3.1.13 Differentiating DC and AC From the Same Signal
      14. 3.1.14 Fluxgate Sensor
    2. 3.2 Software Requirements
      1. 3.2.1 Software Description for Fault Detection
    3. 3.3 Test Setup
      1. 3.3.1 Ground-Fault Simulation
    4. 3.4 Test Results
      1. 3.4.1 Linearity Over Temperature
    5. 3.5 Fault Response Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author

3.1.6 DC Offset Circuit

In place of 0 Ω R23, a DC offset circuit was used. The auto-oscillation duty cycle was found to be 50.10% at steady state with no fault condition. For the best case, the duty cycle is 50.00% with no fault condition. This duty-cycle shift resulted in a consistent 200-mV DC offset evident on the final output of the filter stage. The DC offset is an issue,because thresholds for positive and negative fault current are not the same. By zeroing the AC_SENSING output, both negative and positive ground fault current have the same threshold. This offset is due to the magnetic core and can vary depending on material used.

Figure 3-10 shows the schematic for the dual-supply, inverting amplifier circuit configuration.



Figure 3-10 Dual-Supply, Inverting Amplifier Circuit Schematic

The inverting op-amp configuration takes an input signal that is applied directly to the inverting input terminal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is that the topology avoids common-mode limitations. The load resistance for this topology is equal to R2. The values of the resistors in the feedback network determine the amount of gain to amplify the input signal.

Equation 4 displays the transfer function for the dual-supply, inverting amplifier circuit configuration with level shifting input shown in Figure 3-10.

Equation 4. V O U T = - R 1 R 2 V I N + 1 + R 1 R 2 R 4 R 3 + R 4 V R E F

Capacitor C2 filters noise that can be introduced from the VREF input. Equation 5 calculates the cutoff frequency due to C2.

Equation 5. f C _ V r e f = 1 2 π × R 3 / / R 4 × C 2

Capacitor C4 provides the option to filter the output. The cutoff frequency of the filter can be calculated using Equation 6.

Equation 6. f C _ V o u t = 1 2 π × R 1 × C 4