TIDUF13 November   2022 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Signal-Chain Voltage Levels
        1.       12
      2. 2.2.2 ADC Configuration
      3. 2.2.3 ADC Clocking and Synchronization
      4. 2.2.4 Differential Low-Pass Filter
      5. 2.2.5 Current Source
      6. 2.2.6 Gain Stage and High-Pass Filter
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L11
      2. 2.3.2 THS4551
  8. 3System Design Theory
    1. 3.1 IEPE Sensor
      1. 3.1.1 IEPE Sensor Parameters
        1. 3.1.1.1 Sensitivity and Measurement Range
        2. 3.1.1.2 Excitation, Output Bias Voltage, and Output Impedance
        3. 3.1.1.3 Linearity and Temperature Variance
        4. 3.1.1.4 Frequency Response
        5. 3.1.1.5 Noise and Dynamic Range
  9. 4Hardware, Software, Testing, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 Board Interface
      2. 4.1.2 Power Configuration
        1. 4.1.2.1 Power Sequence
        2. 4.1.2.2 Analog Supply
        3. 4.1.2.3 Digital Supply
        4. 4.1.2.4 Excitation Current Supply
        5. 4.1.2.5 SPI Connectivity Modes and Their Assembly Variants
          1. 4.1.2.5.1 Daisy-Chain Mode
          2. 4.1.2.5.2 Parallel SDO Mode
          3. 4.1.2.5.3 Parallel SDI Mode and Parallel SDO Mode
          4. 4.1.2.5.4 Clocking Modes
    2. 4.2 Software Requirements
    3. 4.3 Test Setup and Procedure
      1. 4.3.1 Noise Floor and SNR
      2. 4.3.2 Gain and Input Range
      3. 4.3.3 Crosstalk
      4. 4.3.4 Total Harmonic Distortion
      5. 4.3.5 Clock Image Rejection
      6. 4.3.6 Synchronization of the ADCs
      7. 4.3.7 Fault Detection Circuit
    4. 4.4 Test Results
      1. 4.4.1 Noise Floor and Dynamic Range
      2. 4.4.2 Gain and Input Range
      3. 4.4.3 Crosstalk
      4. 4.4.4 Total Harmonic Distortion
      5. 4.4.5 Clock Image Rejection
      6. 4.4.6 Synchronization of the ADCs
      7. 4.4.7 Fault Detection Circuit
      8. 4.4.8 Test With Actual IEPE Sensor
      9. 4.4.9 Measurement Results Summary
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  11. 6About the Author

1.1 Key System Specification

This reference design is intended for high-end multichannel wideband high-resolution, high-sampling-rate interfaces. Four channels are demonstrating the concept that can be extended to 6 or more channels. The standard IEPE sensors require excitation current > 2 mA and excitation voltage > 22 V and bandwidth > 15 kHz for most applications. The design supports two SPI communication modes:

  1. Daisy-chain mode, which enables all ADC devices to connect to a single SPI channel, minimizing the control lines and isolation signals, if applied
  2. Parallel mode, which enables the ADCs to run at their maximum data rate but requires a separate data output line per ADC

The low-power consumption enables the design to be used in battery-powered monitoring systems. Wire-break and short-circuit detection is designed for safe and reliable operation of the sensor interface.

Table 1-1 Key System Specifications
PARAMETERSPECIFICATIONS
Number of channels4

Input signal

±10 V, single-ended

Coupling

AC coupled

Excitation voltage23 V (minimum)
Excitation current

3.5 mA

Resolution24 bits
Bandwidth0.6 Hz to 20 kHz
Data rate124 kSPS per channel wideband filter, daisy chain SPI
400 kSPS per channel wideband filter, parallel SPI
1000 kSPS per channel sinc filter, parallel SPI
Target SNR> 100 dB
Gain

0.4 V/V

Sampling clock frequency

16 MHz

SPI clock frequency16 MHz
Input impedance> 250 kΩ

Power consumption

< 1 W

Operating temperature–40°C to 125°C
Diagnostic featuresWire-break and short circuit