TIDUF21A December   2022  – January 2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Description of Control Logic
      2. 2.2.2 Behavior Throughout Charge Cycle
      3. 2.2.3 Additional Design Recommendations
      4. 2.2.4 Simulation Results
    3. 2.3 Highlighted Products
      1. 2.3.1 TPSI3052-Q1
      2. 2.3.2 TLV7011
      3. 2.3.3 UCC27517A-Q1
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Authors
  11. 6Revision History

2.3.1 TPSI3052-Q1

The TPSI3052-Q1 is a fully integrated, isolated switch driver, which when combined with an external power switch, forms a complete isolated solid-state relay (SSR) replacement. With a nominal gate drive voltage of 15-V and 1.5/3.0-A peak source and sink current, a large variety of external power switches can be chosen to meet a wide range of applications. The TPSI3052-Q1 generates its own secondary bias supply from the power received from its primary side, so no discrete isolated bias power supply is required. Additionally, the TPSI3052-Q1 can optionally supply power to external supporting circuitry for various application needs. In three-wire mode, the primary supply of 3-V to 5.5-V is supplied externally, and the switch is controlled through a separate enable.

TPSI3052-Q1 features:

  • Adjustable power transfer
  • Integrated 15-V gate supply
  • Up to 50-mW supply to power auxiliary circuitry (IAUX)

  • UVLO to prevent switching when the supply voltage is too low

For the primary side, TPSI3052-Q1 is set to three-wire mode configuration to achieve the highest power transfer available. Using a 20-kΩ resistor with a 1 % tolerance in PXFR pin provides the highest power transfer available and supports up to 50-mW of IAUX. It is recommended to add a 1-uF in parallel with a 0.1-uF ceramic capacitor with low ESR to VDDP.

For the secondary side, CDIV1 (C3) and CDIV2 (C4, C5) capacitors need to be properly selected to drive the back to back MOSFETs. If CDIV1 and CDIV2 are too small, then the voltage drop in VDDH will trigger an undervoltage lockout (UVLO) and disable the driver. The following two equations can be used for calculating the proper capacitance values.

Equation 21. CDIV1 = (n+1n) ×QLOAD∆V, n≥1.0
Equation 22. CDIV2 = n × CDIV1, n≥1.0
  • n is a real number greater than or equal to 1.0.
  • CDIV1 is the external capacitance from VDDH to VDDM.
  • CDIV2 is the external capacitance from VDDM to VSSS.
  • QLOAD is the total charge of the load from VDRV to VSSS.
  • ΔV is the voltage drop on VDDH when switching the load.

The MOSFETs selected for this design each have a gate charge (QG) of 55-nC. Since the TPSI3052-Q1 needs to power other devices for the control logic. The, CDIV2 = 3 x CDIV1, then CDIV1 is selected with capacitance of 10-uF to make sure that VDDH voltage drop is less than 1-V. Use this excel calculator to calculate for capacitors and power transfer selection.