TIDUF29 October   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Connectors
      2. 2.2.2 High-Speed Traces
      3. 2.2.3 Power Rails
    3. 2.3 Highlighted Products
      1. 2.3.1 DS560DF410
      2. 2.3.2 TPS62867
      3. 2.3.3 TPS7A52
      4. 2.3.4 TLV702
      5. 2.3.5 TXB0108
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 TX Output Eye Test
      2. 3.1.2 RX Link Test
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 TX Output Eye Test
      2. 3.3.2 RX Link Test
    4. 3.4 Test Results
      1. 3.4.1 TX Output Eye Test
      2. 3.4.2 RX Link Test
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

Features

  • 8 independent channels for each direction
  • QSFP-DD cable compatibility, for both ingress and egress
  • Host-side Huber-Suhner and SMA compatibility, for both ingress and egress
  • Configurable through electrically erasable programmable read-only memory (EEPROM) or USB-to-I2C communication
  • Headers for all relevant debug and configuration pin controls and interrupts
  • Onboard power regulation for 3.3 V → {1.8 V,
    1.2 V} domains