TIDUF34A July   2023  – August 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1  DP83TD510E
      2. 2.3.2  AM2434
      3. 2.3.3  TPS2660
      4. 2.3.4  TPS79801-Q1
      5. 2.3.5  MSP430FR2476
      6. 2.3.6  TLV7031
      7. 2.3.7  ATL431
      8. 2.3.8  LM74700-Q1
      9. 2.3.9  TPS62825A
      10. 2.3.10 TPS61023
      11. 2.3.11 TLVM13630
      12. 2.3.12 LSF0108
  9. 3System Design Theory
    1. 3.1 Power Supply
    2. 3.2 PoDL PD and Coupling Network
    3. 3.3 Sitara Technology Module
    4. 3.4 Boot Mode
    5. 3.5 PHI and BoosterPack Headers
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Boot Switch Configuration
      2. 4.1.2 Reference Design Start-Up
    2. 4.2 Software Requirements
      1. 4.2.1 PD Firmware
      2. 4.2.2 MCU Firmware
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

3.5 PHI and BoosterPack Headers

Two options are implemented to add extensions to this board. The PHI interface allows direct interface to many ADC EVMs. The BoosterPack header allows extensions to a lot of other parts, such as interfaces, motor drivers, ADCs and much more. Also, both interfaces can be used to create custom boards and connect them to SPE.

Both interfaces connect to the programmable real time unit (PRU) through level shifters. The level shifters allow use of either 1.8 Vio or 3.3 Vio, for flexibility. All the IOs can either be used from the PRU or as a system GPIO that can be accessed by and through the processor cores. To change the IO-Voltage, either R46 or R47 needs to be assembled. By default, the IO-Voltage is set to 1.8 V. For further details on changes refer to the schematic.

Figure 3-8 shows the pinout of the BoosterPack headers and Figure 3-9 shows the pinout of the PHI connector.


TIDA-010261 BoosterPack Header Pinout

Figure 3-8 BoosterPack™ Header Pinout

TIDA-010261 PHI Header Pinout

Figure 3-9 PHI Header Pinout