TIDUF59 March   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PFC Inductance Design
      2. 2.2.2 Configuration of CS pin in LMG3622
      3. 2.2.3 AHB Topology and the VCC Design
      4. 2.2.4 LMG2610 for AHB Topology
    3. 2.3 Highlighted Products
      1. 2.3.1 UCC28056
      2. 2.3.2 LMG3622
      3. 2.3.3 LMG2610
  9. 3Hardware, Test Requirements, and Test Results
    1. 3.1 Hardware
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Switching Waveform
        1. 3.3.1.1 Switching Waveform on the PFC Stage
        2. 3.3.1.2 Switching Waveform on the AHB Stage
      2. 3.3.2 Efficiency Test Result
      3. 3.3.3 Thermal Test Result
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints {Optional Section}
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.3 AHB Topology and the VCC Design

The DC-DC stage was designed with AHB topology. The DC transfer function of AHB is similar to buck topology and Equation 8 shows the transfer function.

Equation 8. V O U T V I N = D u t y N P S

where

  • NPS is the turn ratio between primary and secondary side

According to the transfer function, the system can only run when

Equation 9. V I N > N P S × V O U T

For better standby power and efficiency, turn off the PFC stage at low voltage and low power condition. Based on this application design, the turns ratio is 5.5, and VOUT × NPS is 154V which can be higher than the VIN voltage (the maximum voltage at 90Vac is 127V) and the system does not operate correctly.

For normal operation the system is designed to power on the PFC stage during the start-up condition for period of time, and then turn off the PFC stage when the VOUT is set as 5V or 9V.

Figure 2-5 shows the design concept by using 2pcs N-channel signal MOSFET as a load switch for the VCC of the PFC stage. Through the 4s RC delay plus the start-up time of the AUX voltage, the PFC is powered on to make the AHB operate normally. The PFC remains turned on when the VOUT > 12V when the output voltage is stable to pull the optotransistor low, but power off the PFC stage when the VOUT < 12V.

In Figure 2-5 the VCC load switch is designed to turn on the PFC stage for a period of time to make sure the whole system powers on successfully.

GUID-20231211-SS0I-8DTC-PRK1-NQ4NRCZLD4K9-low.svg Figure 2-5 VCC Load Switch Design for the PFC Stage