TIDUF59 March   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PFC Inductance Design
      2. 2.2.2 Configuration of CS pin in LMG3622
      3. 2.2.3 AHB Topology and the VCC Design
      4. 2.2.4 LMG2610 for AHB Topology
    3. 2.3 Highlighted Products
      1. 2.3.1 UCC28056
      2. 2.3.2 LMG3622
      3. 2.3.3 LMG2610
  9. 3Hardware, Test Requirements, and Test Results
    1. 3.1 Hardware
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Switching Waveform
        1. 3.3.1.1 Switching Waveform on the PFC Stage
        2. 3.3.1.2 Switching Waveform on the AHB Stage
      2. 3.3.2 Efficiency Test Result
      3. 3.3.3 Thermal Test Result
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints {Optional Section}
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.4 LMG2610 for AHB Topology

AHB is a half-bridge topology which provides the ZVS for the system. With proper design, the system can operate at around 50% duty cycle with lower the RMS current which means lower conduction loss. The best practice is to choose a higher RDS(on) device with lower CO(TR) to optimize the design.

Before the system starts-up, the system must turn on the low-side device to charge the high-side bootstrap capacitor and reset CRES. When the system starts-up, the output voltage is 0V which means the magnetic inductance can be simulated as a shorted circuit and the system total inductance is LRES only. The system suffers high reset current if the CRES is not discharged properly. The system must put the main switching device at the high side.

GUID-20231218-SS0I-V7LJ-MHX0-VD07XLTTRKKM-low.svg Figure 2-6 AHB Equivalent Circuit During Start-Up

The higher RDS(on) device with lower current limit inside the device helps to limit the charge voltage of CRES, which reduces the reset current at the low side. Figure 2-7 shows the waveform of the start-up current. The channel setting is:

  • Ch1: SW voltage of U102 (LMG2610)
  • CH4: The transformer current
GUID-20231214-SS0I-2VDN-NN2S-3CZPC4PXSWLQ-low.svg Figure 2-7 Start-Up Waveform With VOUT is set as 28V and 5A Load Current

In Figure 2-7, the lower current limit of the high-side device prevents charging the CRES too fast during the system start-up.

Before the system is stable, the low-side reset current is higher than the static state. Chooses lower RDS(on) to prevent the OCP was triggered and CRES reset properly.

Figure 2-8 illustrates a lower RDS(on) is chosen to prevent the OCP from triggering and CRES is reset properly.

GUID-20231214-SS0I-G3F5-ZTBR-D21GDKJ5JXSW-low.svg Figure 2-8 Start-Up Waveform With VOUT is set as 28V and 5A Load Current

In this case, LMG2610 is an excellent match with the AHB topology with higher RDS(on) at the high side (248mΩ) and lower resistance at the low side (170mΩ) to balance the performance, and the cost.