TIDUFC1A November   2025  – February 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L21B
      2. 2.3.2 REF81
      3. 2.3.3 REF54
      4. 2.3.4 RES21A
      5. 2.3.5 THP210
      6. 2.3.6 OPA828
  9. 3System Design Theory
    1. 3.1 Range Selection
    2. 3.2 Linearity and Low-Noise Signal Chain
    3. 3.3 Calibration
    4. 3.4 Additional System Design Considerations
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 PCB Interface
      2. 4.1.2 Input Multiplexer
      3. 4.1.3 Gain Multiplexer
      4. 4.1.4 Power Supplies
      5. 4.1.5 Clock Tree
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Integral Nonlinearity Measurements
      2. 4.4.2 Noise Simulation
      3. 4.4.3 Noise Measurements
      4. 4.4.4 Conclusion
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

4.4 Test Results

The following ADC settings are used for the noise and linearity tests:

Table 4-4 GUI Settings
SETTINGSELECTIONGUI LOCATION
REF_RNGHigh-reference rangeRegister Map Config - CONFIG1
CLK_SELInternal clock operationRegister Map Config - CONFIG3
VREF4.096VInterface Configuration
Speed ModeHigh speedInterface Configuration
Filter TypeSinc4+Sinc1Interface Configuration
OSR26667Interface Configuration
CLK DividerDivide by 8Interface Configuration
CLK SourceExternalClock Settings
CLK Frequency25.6MHzClock Settings
SCLK SourceInternal (PHI)Clock Settings
SCLK Frequency25.6MHzClock Settings
Samples1024Interface Configuration

Locate the clock settings by pressing the gear icon next to the SCLK and MCLK frequencies, as shown in Figure 4-7. Any settings not shown in Table 4-4 are left at the GUI default settings. The calculated data rate is set to 60SPS with these changes. Use an external clock source to test other data rates, such as 10PLC (power line cycles) or 0.1PLC. Use connector J22 and move JP5 to the 1–2 position to connect an external clock source. See Section 4.1.5 for more details.