TIDUFC1A November   2025  – February 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L21B
      2. 2.3.2 REF81
      3. 2.3.3 REF54
      4. 2.3.4 RES21A
      5. 2.3.5 THP210
      6. 2.3.6 OPA828
  9. 3System Design Theory
    1. 3.1 Range Selection
    2. 3.2 Linearity and Low-Noise Signal Chain
    3. 3.3 Calibration
    4. 3.4 Additional System Design Considerations
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 PCB Interface
      2. 4.1.2 Input Multiplexer
      3. 4.1.3 Gain Multiplexer
      4. 4.1.4 Power Supplies
      5. 4.1.5 Clock Tree
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Integral Nonlinearity Measurements
      2. 4.4.2 Noise Simulation
      3. 4.4.3 Noise Measurements
      4. 4.4.4 Conclusion
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

4.1.1 PCB Interface

Figure 4-2 shows the PCB connectors. Access the digital interface through J15, which connects to the PHI controller, or through J16, a pin header. J16 has a row of connections to ground, to enable easy connection for an oscilloscope or logic analyzer. The reference design requires an external power supply to operate, which is supplied at J21. Pin headers are used to select the input and set the gain of the programmable gain amplifier.

TIDA-010970 PCB ConnectorsFigure 4-2 PCB Connectors
Table 4-1 TIDA-010970 External Connections
CONNECTORDESCRIPTION
J1SMA connector for input signal
J2Header connector for input signal
J3, J4, J5, J6, J7Enable and input selection headers for the input multiplexer (U7). See Table 4-2 for more details
J10Header for THP210 shutdown
J11, J12, J13, J14Enable and input selection headers for the gain multiplexer. See Table 4-3 for more details
J15QSH connector to connect to PHI, best practice is to power the PCB before connection
J16SPI signals header, use for debugging and probing, or to connect to another board (if no QSH)
JP1EEPROM enable
JP21–2: External IOVDD signal
2–3: IOVDD signal generated by TPS7A47
JP3LDO enable
JP41–2: Selects onboard clock for ADC CLK pin
2–3: Selects PHI clock for ADC CLK pin
JP51–2: Selects external clock as onboard clock
2–3: Selects local oscillator (Y1) as onboard clock

This reference design is intended to operate with a Precision Host Interface (PHI) board, allowing for easy connection with the ADS127L21 Graphical User Interface (GUI). Additionally, the PCB includes a header to allow access to the digital signals from the ADC with an external controller. See also Figure 4-2 for all the PCB connections.