TIDUFC1A November   2025  – February 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L21B
      2. 2.3.2 REF81
      3. 2.3.3 REF54
      4. 2.3.4 RES21A
      5. 2.3.5 THP210
      6. 2.3.6 OPA828
  9. 3System Design Theory
    1. 3.1 Range Selection
    2. 3.2 Linearity and Low-Noise Signal Chain
    3. 3.3 Calibration
    4. 3.4 Additional System Design Considerations
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 PCB Interface
      2. 4.1.2 Input Multiplexer
      3. 4.1.3 Gain Multiplexer
      4. 4.1.4 Power Supplies
      5. 4.1.5 Clock Tree
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Integral Nonlinearity Measurements
      2. 4.4.2 Noise Simulation
      3. 4.4.3 Noise Measurements
      4. 4.4.4 Conclusion
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

Input Multiplexer

The reference design has three input ranges, ±100mV, ±1V, and ±10V that can calibrated. Select between the input signal and the calibration sources using the 8-channel input multiplexer (U1). Jumpers J3, J4, J5, and J6 enable the input multiplexer and select the desired input channel. See Table 4-2 for details.

Table 4-2 Jumper Settings for Input Multiplexer
J3 (EN)J4 (A2)J5 (A1)J6 (A0)INPUT CHANNEL
0X(1)X(1)X(1)None, U1 disabled
1000Input signal
100110V range calibration signal
10101V range calibration signal
1011100mV range calibration signal
11X(1)X(1)Ground
'X' denotes a 'Don't Care'.
TIDA-010970 Input Multiplexer
                    Schematic Figure 4-3 Input Multiplexer Schematic