TIDUFH2 March   2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Loop Bandwidth
      2. 2.2.2 Fast Setting and Sampling
      3. 2.2.3 Low Temperature Drift and Long-Term Drift
      4. 2.2.4 Output Capacity
      5. 2.2.5 Linearity
      6. 2.2.6 Current Leakage
      7. 2.2.7 Reduce Noise
      8. 2.2.8 Reduce Glitch When Switching Current Range
      9. 2.2.9 Heat Design
        1. 2.2.9.1 OPA593
        2. 2.2.9.2 OPA593 Divider Resistor and Series Resistor
        3. 2.2.9.3 Current Sensing Resistor and Feedback Voltage Divider
        4. 2.2.9.4 Clamp Resistor
    3. 2.3 Highlighted Products
      1. 2.3.1  REF54
      2. 2.3.2  DAC11001B
      3. 2.3.3  DAC80502
      4. 2.3.4  ADS9317
      5. 2.3.5  OPA593
      6. 2.3.6  OPA596
      7. 2.3.7  PGA849
      8. 2.3.8  OPA454
      9. 2.3.9  OPA4187
      10. 2.3.10 THS4552
      11. 2.3.11 RES11A
  9. 3System Design Theory
    1. 3.1 Force Voltage Mode
    2. 3.2 Force Current Mode
    3. 3.3 Buffer Mode
    4. 3.4 Gang_Master Mode
    5. 3.5 Gang_Slaver Mode
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Support Working Mode
      2. 4.1.2 Power Supply
      3. 4.1.3 Hardware Connection
    2. 4.2 Software Requirements
      1. 4.2.1 PC GUI
        1. 4.2.1.1 Control Window
        2. 4.2.1.2 ADC Read Raw Data Window
        3. 4.2.1.3 Calibration Window
    3. 4.3 Test Setup
      1. 4.3.1 Source Mode Connection
      2. 4.3.2 Sink Mode Connection
      3. 4.3.3 Gang Mode Connection
    4. 4.4 Test Results
      1. 4.4.1 Linearity and Accuracy
        1. 4.4.1.1 FV ±40V, 500mA, Comp = 10k+470nF, DUT = 3MΩ
        2. 4.4.1.2 FV, 0V to 80V, 500mA, Comp = 10k+470nF, DUT = 3MΩ
        3. 4.4.1.3 FI, ±40V, 10mA, Comp = 10k + 470nF, DUT = 3MΩ
        4. 4.4.1.4 Buffer, ±40V, 10mA, Comp = 10k + 470nF, DUT = 3MΩ
      2. 4.4.2 Transient
      3. 4.4.3 Capacitance Load
      4. 4.4.4 Glitch
      5. 4.4.5 Settling Time
      6. 4.4.6 ADC Swing LSB
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 Layout Prints
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Acknowledgment

Description

This reference design presents a four-quadrant discrete floating Voltage and Current (VI) design. Voltage output supports ±40V and 0V to 80V ranges, with three current ranges of 500mA, 10mA, and 10μA. The design operates on force voltage (FV), force current (FI), Buffer, and Gang mode with analog feedback loop. With 20-bit force digital-to-analog converter (DAC) and 18-bit, 2-channel analog-to-digital converter (ADC) and precision signal chain, the reference design achieves 0.01% accuracy for controlling and measuring after calibration.