SNAS734E July   2017  – January 2020 CDCI6214

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Example CDCI6214
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
          1. 8.3.3.1.1 Clock Distribution Pre-Scaler Dividers
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
    6. 8.6 Register Maps
      1. 8.6.1 CDCI6214 Registers
        1. 8.6.1.1  GENERIC0 Register (Address = 0h) [reset = 0h]
          1. Table 17. GENERIC0 Register Field Descriptions
        2. 8.6.1.2  GENERIC1 Register (Address = 1h) [reset = 6A32h]
          1. Table 18. GENERIC1 Register Field Descriptions
        3. 8.6.1.3  GENERIC2 Register (Address = 2h) [reset = 53h]
          1. Table 19. GENERIC2 Register Field Descriptions
        4. 8.6.1.4  GENERIC3 Register (Address = 3h) [reset = 0h]
          1. Table 20. GENERIC3 Register Field Descriptions
        5. 8.6.1.5  POWER0 Register (Address = 4h) [reset = 54h]
          1. Table 21. POWER0 Register Field Descriptions
        6. 8.6.1.6  POWER1 Register (Address = 5h) [reset = 30h]
          1. Table 22. POWER1 Register Field Descriptions
        7. 8.6.1.7  STATUS0 Register (Address = 6h) [reset = 0h]
          1. Table 23. STATUS0 Register Field Descriptions
        8. 8.6.1.8  STATUS1 Register (Address = 7h) [reset = 0h]
          1. Table 24. STATUS1 Register Field Descriptions
        9. 8.6.1.9  STATUS2 Register (Address = 8h) [reset = 0h]
          1. Table 25. STATUS2 Register Field Descriptions
        10. 8.6.1.10 STATUS3 Register (Address = 9h) [reset = 0h]
          1. Table 26. STATUS3 Register Field Descriptions
        11. 8.6.1.11 EEPROM0 Register (Address = Ah) [reset = 0h]
          1. Table 27. EEPROM0 Register Field Descriptions
        12. 8.6.1.12 EEPROM1 Register (Address = Bh) [reset = 0h]
          1. Table 28. EEPROM1 Register Field Descriptions
        13. 8.6.1.13 EEPROM2 Register (Address = Ch) [reset = 0h]
          1. Table 29. EEPROM2 Register Field Descriptions
        14. 8.6.1.14 EEPROM3 Register (Address = Dh) [reset = 0h]
          1. Table 30. EEPROM3 Register Field Descriptions
        15. 8.6.1.15 EEPROM4 Register (Address = Eh) [reset = 0h]
          1. Table 31. EEPROM4 Register Field Descriptions
        16. 8.6.1.16 STARTUP0 Register (Address = Fh) [reset = 37h]
          1. Table 32. STARTUP0 Register Field Descriptions
        17. 8.6.1.17 STARTUP1 Register (Address = 10h) [reset = 921Fh]
          1. Table 33. STARTUP1 Register Field Descriptions
        18. 8.6.1.18 STARTUP2 Register (Address = 11h) [reset = 6C4h]
          1. Table 34. STARTUP2 Register Field Descriptions
        19. 8.6.1.19 REV0 Register (Address = 18h) [reset = 601h]
          1. Table 35. REV0 Register Field Descriptions
        20. 8.6.1.20 INPUT0 Register (Address = 1Ah) [reset = B14h]
          1. Table 36. INPUT0 Register Field Descriptions
        21. 8.6.1.21 INPUT1 Register (Address = 1Bh) [reset = 0h]
          1. Table 37. INPUT1 Register Field Descriptions
        22. 8.6.1.22 INPUT_DBG0 Register (Address = 1Ch) [reset = 0h]
          1. Table 38. INPUT_DBG0 Register Field Descriptions
        23. 8.6.1.23 PLL0 Register (Address = 1Dh) [reset = Ch]
          1. Table 39. PLL0 Register Field Descriptions
        24. 8.6.1.24 PLL1 Register (Address = 1Eh) [reset = 5140h]
          1. Table 40. PLL1 Register Field Descriptions
        25. 8.6.1.25 PLL2 Register (Address = 1Fh) [reset = 1E72h]
          1. Table 41. PLL2 Register Field Descriptions
        26. 8.6.1.26 PLL4 Register (Address = 21h) [reset = 7h]
          1. Table 42. PLL4 Register Field Descriptions
        27. 8.6.1.27 CH1_CTRL0 Register (Address = 23h) [reset = 8000h]
          1. Table 43. CH1_CTRL0 Register Field Descriptions
        28. 8.6.1.28 CH1_CTRL1 Register (Address = 24h) [reset = 0h]
          1. Table 44. CH1_CTRL1 Register Field Descriptions
        29. 8.6.1.29 CH1_CTRL2 Register (Address = 25h) [reset = 8003h]
          1. Table 45. CH1_CTRL2 Register Field Descriptions
        30. 8.6.1.30 CH1_CTRL3 Register (Address = 26h) [reset = 9h]
          1. Table 46. CH1_CTRL3 Register Field Descriptions
        31. 8.6.1.31 CH1_CTRL4 Register (Address = 27h) [reset = 679h]
          1. Table 47. CH1_CTRL4 Register Field Descriptions
        32. 8.6.1.32 CH1_CTRL5 Register (Address = 28h) [reset = 8h]
          1. Table 48. CH1_CTRL5 Register Field Descriptions
        33. 8.6.1.33 CH2_CTRL0 Register (Address = 29h) [reset = 8000h]
          1. Table 49. CH2_CTRL0 Register Field Descriptions
        34. 8.6.1.34 CH2_CTRL1 Register (Address = 2Ah) [reset = 0h]
          1. Table 50. CH2_CTRL1 Register Field Descriptions
        35. 8.6.1.35 CH2_CTRL2 Register (Address = 2Bh) [reset = 0h]
          1. Table 51. CH2_CTRL2 Register Field Descriptions
        36. 8.6.1.36 CH2_CTRL3 Register (Address = 2Ch) [reset = 8h]
          1. Table 52. CH2_CTRL3 Register Field Descriptions
        37. 8.6.1.37 CH2_CTRL4 Register (Address = 2Dh) [reset = 71h]
          1. Table 53. CH2_CTRL4 Register Field Descriptions
        38. 8.6.1.38 CH2_CTRL5 Register (Address = 2Eh) [reset = 8h]
          1. Table 54. CH2_CTRL5 Register Field Descriptions
        39. 8.6.1.39 CH3_CTRL0 Register (Address = 2Fh) [reset = 8000h]
          1. Table 55. CH3_CTRL0 Register Field Descriptions
        40. 8.6.1.40 CH3_CTRL1 Register (Address = 30h) [reset = 0h]
          1. Table 56. CH3_CTRL1 Register Field Descriptions
        41. 8.6.1.41 CH3_CTRL2 Register (Address = 31h) [reset = 0h]
          1. Table 57. CH3_CTRL2 Register Field Descriptions
        42. 8.6.1.42 CH3_CTRL3 Register (Address = 32h) [reset = 4h]
          1. Table 58. CH3_CTRL3 Register Field Descriptions
        43. 8.6.1.43 CH3_CTRL4 Register (Address = 33h) [reset = 671h]
          1. Table 59. CH3_CTRL4 Register Field Descriptions
        44. 8.6.1.44 CH3_CTRL5 Register (Address = 34h) [reset = 8h]
          1. Table 60. CH3_CTRL5 Register Field Descriptions
        45. 8.6.1.45 CH4_CTRL0 Register (Address = 35h) [reset = 8000h]
          1. Table 61. CH4_CTRL0 Register Field Descriptions
        46. 8.6.1.46 CH4_CTRL1 Register (Address = 36h) [reset = 0h]
          1. Table 62. CH4_CTRL1 Register Field Descriptions
        47. 8.6.1.47 CH4_CTRL2 Register (Address = 37h) [reset = 0h]
          1. Table 63. CH4_CTRL2 Register Field Descriptions
        48. 8.6.1.48 CH4_CTRL3 Register (Address = 38h) [reset = 4h]
          1. Table 64. CH4_CTRL3 Register Field Descriptions
        49. 8.6.1.49 CH4_CTRL4 Register (Address = 39h) [reset = 71h]
          1. Table 65. CH4_CTRL4 Register Field Descriptions
        50. 8.6.1.50 CH4_CTRL5 Register (Address = 3Ah) [reset = 8h]
          1. Table 66. CH4_CTRL5 Register Field Descriptions
        51. 8.6.1.51 CHX_CTRL0 Register (Address = 3Bh) [reset = 61h]
          1. Table 67. CHX_CTRL0 Register Field Descriptions
        52. 8.6.1.52 CHX_CTRL1 Register (Address = 3Ch) [reset = 18h]
          1. Table 68. CHX_CTRL1 Register Field Descriptions
        53. 8.6.1.53 CHX_CTRL2 Register (Address = 3Dh) [reset = 1500h]
          1. Table 69. CHX_CTRL2 Register Field Descriptions
        54. 8.6.1.54 CHX_CTRL3 Register (Address = 3Eh) [reset = 4210h]
          1. Table 70. CHX_CTRL3 Register Field Descriptions
        55. 8.6.1.55 CHX_CTRL4 Register (Address = 3Fh) [reset = 210h]
          1. Table 71. CHX_CTRL4 Register Field Descriptions
        56. 8.6.1.56 DBG0 Register (Address = 42h) [reset = 200h]
          1. Table 72. DBG0 Register Field Descriptions
      2. 8.6.2 EEPROM Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence
    2. 10.2 De-Coupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • One Configurable High Performance, Low-Power PLL With 4 Programmable Outputs
  • RMS Jitter Performance
    • Supports PCIe Gen1/ Gen2 / Gen3 / Gen4 without SSC
  • Typical Power Consumption: 150 mW at 1.8 V(2)
  • Universal Clock Input
    • Differential AC-Coupled or LVCMOS: 1 MHz to 250 MHz
    • Crystal: 8 MHz to 50 MHz
  • Flexible Output Frequencies
    • 44.1 kHz to 350 MHz
    • Glitchless Output Divider Switching
  • Four Individually Configurable Outputs
    • LVCMOS, LVDS or HCSL
    • Differential AC-Coupled With Programmable Swing (LVDS-, CML-, LVPECL-Compatible)
  • Fully Integrated PLL, Configurable Loop Bandwidth: 100 kHz to 3 MHz
  • Single or Mixed Supply Operation for Level Translation: 1.8 V, 2.5 V and 3.3 V
  • Configurable GPIOs
    • Status Signals
    • Up to 4 Individual Output Enables
    • Output Divider Synchronization
  • Flexible Configuration Options
    • I2C-Compatible Interface: Up to 400 kHz
    • Integrated EEPROM With Two Pages and External Select Pin
  • Only Supports 100 Ω Systems
  • Industrial Temperature Range: –40ºC to 85ºC
  • Small Footprint: 24-Pin VQFN (4 mm × 4 mm)