Home Clocks & timing Clock generators
Home
Clocks & timing
Clock generators

CDCI6214

ACTIVE

PCIe Gen4 support ultra-low power clock generator with four programmable outputs & EEPROM

Order now
Data sheet

CDCI6214

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 4 Output frequency (max) (MHz) 350 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Output type HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable, Serial interface Rating Catalog
Function Clock generator Number of outputs 4 Output frequency (max) (MHz) 350 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Output type HCSL, LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable, Serial interface Rating Catalog
VQFN (RGE) 24 16 mm² 4 x 4
  • One Configurable High Performance, Low-Power PLL With 4 Programmable Outputs
  • RMS Jitter Performance
    • Supports PCIe Gen1/ Gen2 / Gen3 / Gen4 without SSC
  • Typical Power Consumption: 150 mW at 1.8 V(2)
  • Universal Clock Input
    • Differential AC-Coupled or LVCMOS: 1 MHz to 250 MHz
    • Crystal: 8 MHz to 50 MHz
  • Flexible Output Frequencies
    • 44.1 kHz to 350 MHz
    • Glitchless Output Divider Switching
  • Four Individually Configurable Outputs
    • LVCMOS, LVDS or HCSL
    • Differential AC-Coupled With Programmable Swing (LVDS-, CML-, LVPECL-Compatible)
  • Fully Integrated PLL, Configurable Loop Bandwidth: 100 kHz to 3 MHz
  • Single or Mixed Supply Operation for Level Translation: 1.8 V, 2.5 V and 3.3 V
  • Configurable GPIOs
    • Status Signals
    • Up to 4 Individual Output Enables
    • Output Divider Synchronization
  • Flexible Configuration Options
    • I2C-Compatible Interface: Up to 400 kHz
    • Integrated EEPROM With Two Pages and External Select Pin
  • Only Supports 100 Ω Systems
  • Industrial Temperature Range: –40ºC to 85ºC
  • Small Footprint: 24-Pin VQFN (4 mm × 4 mm)
  • One Configurable High Performance, Low-Power PLL With 4 Programmable Outputs
  • RMS Jitter Performance
    • Supports PCIe Gen1/ Gen2 / Gen3 / Gen4 without SSC
  • Typical Power Consumption: 150 mW at 1.8 V(2)
  • Universal Clock Input
    • Differential AC-Coupled or LVCMOS: 1 MHz to 250 MHz
    • Crystal: 8 MHz to 50 MHz
  • Flexible Output Frequencies
    • 44.1 kHz to 350 MHz
    • Glitchless Output Divider Switching
  • Four Individually Configurable Outputs
    • LVCMOS, LVDS or HCSL
    • Differential AC-Coupled With Programmable Swing (LVDS-, CML-, LVPECL-Compatible)
  • Fully Integrated PLL, Configurable Loop Bandwidth: 100 kHz to 3 MHz
  • Single or Mixed Supply Operation for Level Translation: 1.8 V, 2.5 V and 3.3 V
  • Configurable GPIOs
    • Status Signals
    • Up to 4 Individual Output Enables
    • Output Divider Synchronization
  • Flexible Configuration Options
    • I2C-Compatible Interface: Up to 400 kHz
    • Integrated EEPROM With Two Pages and External Select Pin
  • Only Supports 100 Ω Systems
  • Industrial Temperature Range: –40ºC to 85ºC
  • Small Footprint: 24-Pin VQFN (4 mm × 4 mm)

The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.

Each of the four output channels has a configurable integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25-MHz LVDS outputs consume 150 mW at 1.8 V. Typical RMS jitter of 386 fs for 100-MHz HCSL output enhances system margin for PCIe applications.

The CDCI6214 is configured using internal registers that are accessed by an I2C-compatible serial interface and internal EEPROM.

The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM make the CDCI6214 ideal as easy-to-use, instant-on clocking solution with low power consumption.

The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.

Each of the four output channels has a configurable integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25-MHz LVDS outputs consume 150 mW at 1.8 V. Typical RMS jitter of 386 fs for 100-MHz HCSL output enhances system margin for PCIe applications.

The CDCI6214 is configured using internal registers that are accessed by an I2C-compatible serial interface and internal EEPROM.

The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM make the CDCI6214 ideal as easy-to-use, instant-on clocking solution with low power consumption.
open-in-new Find other Clock generators
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare products
Pin-for-pin with same functionality to the compared device.
CDCE6214 ACTIVE Ultra-low power clock generator with one PLL, four differential output Pin-to-pin, PCIe-Gen-5-compliant upgrade, LP-HCSL output and fractional PLL support with lower 1ku price
Similar functionality to the compared device.
CDCM6208 ACTIVE 2:8 ultra-low power, low jitter clock generator Ultra-low power, 365-fs RMS (typical), clock generator device for fractional or integer divided differential outputs

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet CDCI6214 Ultra-Low Power Clock Generator With PCIe Support, Four Programmable Outputs and EEPROM datasheet (Rev. E) PDF | HTML 27 Jan 2020
EVM User's guide CDCI6214EVM User’s Guide (Rev. B) 25 Oct 2018
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCI6214EVM — CDCI6214 Ultra-Low Power Clock Generator Evaluation Module

interface to access the I2C bus to communicate with the CDCI6214 as well as its control pins and the power supply. The edge-launch SMA-connectors enable measurements using 50 Ω equipment while the on-board termination allows to use high impedance probes. The flexible re-work options allow to (...)
User guide: PDF
Not available on TI.com
Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Download
Simulation model

CDCI6214 IBIS Model (Rev. A)

SNAM219A.ZIP (349 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
VQFN (RGE) 24 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos