PCIe Gen4 support ultra-low power clock generator with four programmable outputs & EEPROM


Product details


Function Clock generator Number of outputs 4 Output frequency (Max) (MHz) 350 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type XTAL, LVCMOS, Differential Output type LVCMOS, LVDS, LVPECL, HCSL Operating temperature range (C) -40 to 85 Features I2C, Pin programmable, Integrated EEPROM, Serial interface Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

VQFN (RGE) 24 16 mm² 4 x 4 open-in-new Find other Clock generators


  • One Configurable High Performance, Low-Power PLL With 4 Programmable Outputs
  • RMS Jitter Performance
    • Supports PCIe Gen1/ Gen2 / Gen3 / Gen4 without SSC
  • Typical Power Consumption: 150 mW at 1.8 V(2)
  • Universal Clock Input
    • Differential AC-Coupled or LVCMOS: 1 MHz to 250 MHz
    • Crystal: 8 MHz to 50 MHz
  • Flexible Output Frequencies
    • 44.1 kHz to 350 MHz
    • Glitchless Output Divider Switching
  • Four Individually Configurable Outputs
    • Differential AC-Coupled With Programmable Swing (LVDS-, CML-, LVPECL-Compatible)
  • Fully Integrated PLL, Configurable Loop Bandwidth: 100 kHz to 3 MHz
  • Single or Mixed Supply Operation for Level Translation: 1.8 V, 2.5 V and 3.3 V
  • Configurable GPIOs
    • Status Signals
    • Up to 4 Individual Output Enables
    • Output Divider Synchronization
  • Flexible Configuration Options
    • I2C-Compatible Interface: Up to 400 kHz
    • Integrated EEPROM With Two Pages and External Select Pin
  • Only Supports 100 Ω Systems
  • Industrial Temperature Range: –40ºC to 85ºC
  • Small Footprint: 24-Pin VQFN (4 mm × 4 mm)

All trademarks are the property of their respective owners.

open-in-new Find other Clock generators


The CDCI6214 device is an ultra-low power clock generator. The device selects between two independent reference inputs to a phase-locked loop and generates up to four different frequencies on configurable differential output channels and also a copy of the reference clock on a LVCMOS output channel.

Each of the four output channels has a configurable integer divider. Together with the output muxes, this allows up to five different frequencies. Clock distribution dividers are reset in a deterministic way for clean clock gating and glitch-less update capability. Flexible power-down options allow to optimize the device for lowest power consumption in active and standby operation. Typically four 156.25-MHz LVDS outputs consume 150 mW at 1.8 V. Typical RMS jitter of 386 fs for 100-MHz HCSL output enhances system margin for PCIe applications.

The CDCI6214 is configured using internal registers that are accessed by an I2C-compatible serial interface and internal EEPROM.

The CDCI6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM make the CDCI6214 ideal as easy-to-use, instant-on clocking solution with low power consumption.

open-in-new Find other Clock generators
Similar products you might be interested in
open-in-new Compare products
Same functionality and pinout but is not an equivalent to the compared device:
NEW CDCE6214-Q1 ACTIVE Ultra-low power clock generator supporting PCIe gen 1-5 with 2 inputs, 4 outputs and internal EEPROM Use this ultra-low power, 350-fs RMS (typical), clock generator device with one fractional-N PLL to generate multiple output frequencies
Similar but not functionally equivalent to the compared device:
CDCM6208 ACTIVE 2:8 Ultra Low Power, Low Jitter Clock Generator Use this ultra-low power, 365-fs RMS (typical), clock generator device for fractional or integer divided differential outputs

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet CDCI6214 Ultra-Low Power Clock Generator With PCIe Support, Four Programmable Outputs and EEPROM datasheet (Rev. E) Jan. 27, 2020
User guides CDCI6214EVM User’s Guide (Rev. B) Oct. 25, 2018
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
interface to access the I2C bus to communicate with the CDCI6214 as well as its control pins and the power supply. The edge-launch SMA-connectors enable measurements using 50 Ω equipment while the on-board termination allows to use high impedance probes. The flexible re-work options allow to (...)
  • Ultra-low power operation
  • Single high-performance phase-locked-loop
  • Supports mixed power supply operation from 1.8 V to 3.3 V
  • Integrated EEPROM with two pages
  • General purpose inputs and outputs for individual output enable and  status signals
  • Output divider synchronization and digital delays

Software development

Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SNAM219A.ZIP (349 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGE) 24 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​


Related videos