TIDUEP0 May   2020

 

  1.    Description
  2.    Resources
  3.    Features
  4.    Applications
  5. 1Design Images
  6. 2System Description
    1. 2.1 Key System Specifications
  7. 3System Overview
    1. 3.1 Block Diagram
    2. 3.2 Design Considerations
      1. 3.2.1 Small Compact Size
      2. 3.2.2 Transformer less Solution
    3. 3.3 Highlighted Products
      1. 3.3.1  TPD4E05U06 4-Channel Ultra-Low-Capacitance IEC ESD Protection Diode
      2. 3.3.2  TPD2EUSB30 2-Channel ESD Solution for SuperSpeed USB 3.0 Interface
      3. 3.3.3  2.3.3 HD3SS3220 10Gbps USB 3.1 USB Type-C 2:1 MUX With DRP Controller
      4. 3.3.4  TPS54218 2.95V to 6V Input, 2A Synchronous Step-Down SWIFT™ Converter
      5. 3.3.5  TPS54318 2.95V to 6V Input, 3A Synchronous Step-Down SWIFT™ Converter
      6. 3.3.6  CSD19538Q3A 100V, N ch NexFET MOSFET™, single SON3x3, 49mOhm
      7. 3.3.7  LM3488 2.97V to 40V Wide Vin Low-Side N-Channel Controller for Switching Regulators
      8. 3.3.8  TPS61178 20-V Fully Integrated Sync Boost with Load Disconnect
      9. 3.3.9  LMZM23601 36-V, 1-A Step-Down DC-DC Power Module in 3.8-mm × 3-mm Package
      10. 3.3.10 TPS7A39 Dual, 150mA, Wide-Vin, Positive and Negative Low-Dropout (LDO) Voltage Regulator
      11. 3.3.11 TPS74201 Single-output 1.5-A LDO regulator, adjustable (0.8V to 3.3V), any or no cap, programmable soft start
      12. 3.3.12 LP5910 300-mA low-noise low-IQ low-dropout (LDO) linear regulator
      13. 3.3.13 LP5907 250-mA ultra-low-noise low-IQ low-dropout (LDO) linear
      14. 3.3.14 INA231 28V, 16-bit, i2c output current/voltage/power monitor w/alert in wcsp
    4. 3.4 System Design Theory
      1. 3.4.1 Input Section
      2. 3.4.2 Designing of SEPIC based High Voltage Supply
        1. 3.4.2.1  Basic Operation Principle of SEPIC Converter
        2. 3.4.2.2  Design of Dual SEPIC Supply using uncoupled inductors
        3. 3.4.2.3  Duty Cycle
        4. 3.4.2.4  Inductor Selection
        5. 3.4.2.5  Power MOSFET Selection
        6. 3.4.2.6  Output Diode Selection
        7. 3.4.2.7  Coupling Capacitor Selection
        8. 3.4.2.8  Output Capacitor Selection
        9. 3.4.2.9  Input Capacitor Selection
        10. 3.4.2.10 Programming the Output Voltage
      3. 3.4.3 Designing the Low Voltage Power Supply
      4. 3.4.4 Designing the TPS54218 through Webench Power Designer
      5. 3.4.5 ± 5V Transmit Supply Generation
      6. 3.4.6 System Clock Synchronization
      7. 3.4.7 Power and data output connector
      8. 3.4.8 System Current and Power Monitoring
  8. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Testing and Results
      1. 4.1.1 Test Setup
      2. 4.1.2 Test Results
        1. 4.1.2.1 High Voltage Power Supply
        2. 4.1.2.2 Output Ripple Measurement
        3. 4.1.2.3 Load Transient Test
        4. 4.1.2.4 Noise Measurement
        5. 4.1.2.5 Thermal Performance
        6. 4.1.2.6 Low Voltage Power Supply
          1. 4.1.2.6.1 Thermal Performance
          2. 4.1.2.6.2 FX3 Supply
  9. 5Layout Guidelines
    1. 5.1 High-Voltage Supply Layout
    2. 5.2 USB Section Layout Guidelines
  10. 6Design Files
    1. 6.1 Schematics
    2. 6.2 Bill of Materials
    3. 6.3 PCB Layout Recommendations
      1. 6.3.1 Layout Prints
    4. 6.4 Altium Project
    5. 6.5 Gerber Files
    6. 6.6 Assembly Drawings
  11. 7Software Files
  12. 8Related Documentation
    1. 8.1 Trademarks
    2. 8.2 Third-Party Products Disclaimer
  13. 9About the Author

Description

Significant technological advancements and a high degree of integration in medical imaging, especially hand-held ultrasound smart probes, are pushing engineers to come up with highly efficient, noise-immune power systems in a small size. This reference design documents end-to-end power and data acquisition, for our high-performance 128-channel transmitter and 64-channel receiver design (Highly Integrated Signal Chain Solutions TX7332 and AFE5832LP for Smart Ultrasound Probes). The power tree includes a single-stage transformer-less high-voltage generation (± 80 V and height <5mm) for transmit and the point-of-load low-voltage for the AFEs & FPGA from a 5 V USB Type-C™. This reference design enables low-noise (< 10mV ripple), efficient rails and better thermal performance (< 10°C temperature rise) achieving system efficiency – 80%, receive data SNR > 55dB and ultra-compact size (90mm by 45mm by 20mm). All power rails can be synchronized to an external clock using our integrated buffer-divider CDCE949. This design also supports 1-S battery input with a normal ultrasound operation of up to 2 hours.