SLLSFE2
June 2019
SN65HVDA1040B-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Power Dissipation Characteristics
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Operating Modes
8.3.1.1
Bus States by Mode
8.3.1.2
Normal Mode
8.3.1.3
Standby Mode and RXD Wake-Up Request
8.3.2
Protection Features
8.3.2.1
TXD Dominant State Time-Out
8.3.2.2
Thermal Shutdown
8.3.2.3
Undervoltage Lockout and Unpowered Device
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Using With 3.3-V Microcontrollers
9.1.2
Using SPLIT With Split Termination
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Bus Loading, Length, and Number of Nodes
9.2.1.2
CAN Termination
9.2.1.3
Loop Propagation Delay
9.2.2
Detailed Design Procedure
9.2.2.1
Transient Voltage Suppresser (TVS) Diodes
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
ESD Protection
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sllsfe2_oa
sllsfe2_pm
1
Features
AEC-Q100 Qualified for automotive applications
Temperature grade 0: –40°C to +125°C, T
A
HBM ESD classification level:
3A Level for all pins except 5, 6, and 7
3B Level for pins 5, 6 and 7
CDM ESD classification level C6
Meets or exceeds the requirements of ISO 11898-2 and -5
GIFT/ICT compliant
Low-current standby mode with bus wakeup, <12 µA maximum
High electromagnetic compliance (EMC)
SPLIT voltage source for common-mode stabilization of bus through split termination
Digital inputs compatible with 3.3-v and 5-v microprocessors
Package options: SOIC
Protection features
Bus-fault protection of –27 V to 40 V
TXD dominant time-out
Thermal shutdown protection
Power up and power down glitch-free bus inputs and outputs
High bus input impedance with low V
CC
(ideal passive behavior on bus when unpowered)