SLASET3C April   2019  – March 2021 TAS2563

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2C Timing Requirements
    7. 6.7  SPI Timing Requirements
    8. 6.8  PDM Port Timing Requirements
    9. 6.9  TDM Port Timing Requirements
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PurePath Console 3 Software
      2. 8.3.2  Device Mode and Address Selection
      3. 8.3.3  General I2C Operation
      4. 8.3.4  General SPI Operation
      5. 8.3.5  Single-Byte and Multiple-Byte Transfers
      6. 8.3.6  Single-Byte Write
      7. 8.3.7  Multiple-Byte Write and Incremental Multiple-Byte Write
      8. 8.3.8  Single-Byte Read
      9. 8.3.9  Multiple-Byte Read
      10. 8.3.10 Register Organization
      11. 8.3.11 Operational Modes
        1. 8.3.11.1 Hardware Shutdown
        2. 8.3.11.2 Software Shutdown
        3. 8.3.11.3 Mute
        4. 8.3.11.4 Active
        5. 8.3.11.5 Perform Load Diagnostics
        6. 8.3.11.6 Mode Control and Software Reset
      12. 8.3.12 Faults and Status
      13. 8.3.13 Digital Input Pull Downs
    4. 8.4 Device Functional Modes
      1. 8.4.1 PDM Input
      2. 8.4.2 TDM Port
      3. 8.4.3 Playback Signal Path
        1. 8.4.3.1 Digital Signal Processor
        2. 8.4.3.2 High Pass Filter
        3. 8.4.3.3 Digital Volume Control and Amplifier Output Level
        4. 8.4.3.4 Auto-mute During Idle Channel Mode
        5. 8.4.3.5 Auto-start/stop on Audio Clocks
        6. 8.4.3.6 Supply Tracking Limiters with Brown Out Prevention
        7. 8.4.3.7 Class-D Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5 Boost
      6. 8.4.6 IV Sense
      7. 8.4.7 Load Diagnostics
      8. 8.4.8 Clocks and PLL
      9. 8.4.9 Thermal Foldback
    5. 8.5 Register Maps
      1. 8.5.1  Register Summary Table Page=0x00
      2. 8.5.2  PAGE (page=0x00 address=0x00) [reset=0h]
      3. 8.5.3  SW_RESET (page=0x00 address=0x01) [reset=0h]
      4. 8.5.4  PWR_CTL (page=0x00 address=0x02) [reset=Eh]
      5. 8.5.5  PB_CFG1 (page=0x00 address=0x03) [reset=20h]
      6. 8.5.6  MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
      7. 8.5.7  MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
      8. 8.5.8  TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
      9. 8.5.9  TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
      10. 8.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
      11. 8.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
      12. 8.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
      13. 8.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
      14. 8.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
      15. 8.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
      16. 8.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
      17. 8.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
      18. 8.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
      19. 8.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
      20. 8.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
      21. 8.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
      22. 8.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
      23. 8.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
      24. 8.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
      25. 8.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
      26. 8.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
      27. 8.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
      28. 8.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
      29. 8.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
      30. 8.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
      31. 8.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
      32. 8.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
      33. 8.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
      34. 8.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
      35. 8.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
      36. 8.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
      37. 8.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
      38. 8.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
      39. 8.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
      40. 8.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
      41. 8.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
      42. 8.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
      43. 8.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
      44. 8.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
      45. 8.5.45 MISC (page=0x00 address=0x32) [reset=80h]
      46. 8.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
      47. 8.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
      48. 8.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
      49. 8.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
      50. 8.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
      51. 8.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
      52. 8.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
      53. 8.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
      54. 8.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
      55. 8.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
      56. 8.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
      57. 8.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
      58. 8.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
      59. 8.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
      60. 8.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
      61. 8.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
      62. 8.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Mono/Stereo Configuration
        2. 9.2.2.2 Boost Converter Passive Devices
        3. 9.2.2.3 EMI Passive Devices
        4. 9.2.2.4 Miscellaneous Passive Devices
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Power Supply Sequencing
      1. 10.2.1 Boost Supply Details
      2. 10.2.2 External Boost Mode (Boost Bypass Mode)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|42
  • RPP|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Key Features
    • 11.5 V, 12-step Look-Ahead Class-H boost
    • Integrated DSP
    • Full Scale Ultrasonic Output to 40kHz
    • 2 PDM Microphone inputs
  • Powerful Class-D Audio Amplifier :
    • 6.1 W 1% THD+N (4 Ω, 3.6 V)
    • 5 W 1% THD+N (8 Ω, 3.6 V)
    • 10 W 1% THD+N (4 Ω, 12 V)
  • Protection Features:
    • Real-Time I/V-Sense Speaker Protection
    • Speaker Thermal & Over-Excursion Protection
    • Short and Open Load Protection
    • Thermal and Over-Current Protection
  • Advanced Audio Processing
    • Dedicated Real-Time DSP with:
      • 10-Band Equalizer
      • 3-Band Dynamic EQ
      • Dynamic Range Compression
      • Psychoacoustic Bass
  • Flexible Interfaces and Control :
    • I2S/TDM: 8 Channels of 32 Bit up to 96 KSPS
    • I2C: Selectable Addresses with Fast Mode+
    • Inter-Chp Communication Bus (DSBGA)
    • 8 kHz to 96 kHz Sample Rates
  • Power Efficiency and Flexibility :
    • 83.5% Efficiency at 1W
    • <1uA HW Shutdown VBAT Current
    • Boost-Bypass Mode
  • Power Supplies and Management
    • VBAT: 2.5 V to 5.5 V
    • VDD: 1.62 V to 1.95 V
    • PVDD: VBAT to 13 V (QFN)
    • PVDD: VBAT to 16 V (DSBGA)
    • IOVDD: 1.65 V to 3.6 V
    • VBAT Tracking Peak Voltage Limiter
    • Advanced Brown Out Prevention