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CDCVF2310-EP

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Enhanced Product 2.5-V to 3.3-V high performance clock buffer

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Data sheet

CDCVF2310-EP

ACTIVE
Data sheet Order now

Product details

Number of outputs 10 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVTTL Input type LVTTL
Number of outputs 10 Additive RMS jitter (typ) (fs) 45 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm)
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP

The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –55°C to 125°C.

The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –55°C to 125°C.
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Top documentation Type Title Format options Date
* Data sheet CDCVF2310-EP 2.5-V to 3.3-V High Performance Clock Buffer datasheet Dec 28, 2012
* Radiation & reliability report CDCVF2310MPWEP Relability Report Feb 9, 2016
* Radiation & reliability report CDCVF2310MPWREP Reliability Report Feb 9, 2016
* VID CDCVF2310-EP VID V6213603 Jun 21, 2016

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