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SN74CBT3126

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5-V, 1:1 (SPST), 4-channel general-purpose FET bus switch with st&ard '126-type pinout

Data sheet
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5-V, 1:1 (SPST), 4-channel general-purpose FET bus switch with st&ard '126-type pinout

SN74CBT3126

ACTIVE
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Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 5 Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (C) -40 to 85 Features Supports JTAG signals, Supports SPI signals Input/output continuous current (Max) (mA) 128 Rating Catalog open-in-new Find other Analog switches & muxes

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SSOP (DB) 14 48 mm² 6.2 x 7.8 SSOP (DBQ) 16 29 mm² 4.9 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Analog switches & muxes

Features

  • Standard ’126-Type Pinout (D, DB, DGV, and PW Packages)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

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Description

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 27
Type Title Date
* Datasheet SN74CBT3126 datasheet (Rev. K) Oct. 06, 2003
Application note Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application note Multiplexers and Signal Switches Glossary Mar. 06, 2020
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature CBT RAID Application Clip Jun. 12, 2003
Application note Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Flexible Voltage-Level Translation With CBT Family Devices Jul. 20, 1999
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) Dec. 01, 1998
Application note 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A) Apr. 03, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B) Mar. 01, 1997
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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Hardware development

INTERFACE ADAPTER Download
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


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CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
SSOP (DB) 14 View options
SSOP (DBQ) 16 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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