SN74LS175 Quadruple D-Type Flip-Flops With Clear | TI.com

SN74LS175
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Quadruple D-Type Flip-Flops With Clear

Quadruple D-Type Flip-Flops With Clear - SN74LS175
Datasheet
 

Description

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

Features

  • '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
  • '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
  • Three Performance Ranges Offered: See Table Lower Right
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74LS175 Order now LS     Bipolar     Push-Pull     4.75     5.25     4     35     18000     8     -0.4     High speed (tpd 10-50ns)     Catalog     PDIP | 16
SOIC | 16
SO | 16    
SN54LS175 Samples not available LS     Bipolar     Push-Pull     4.5     5.5     4     35     18000     8     -0.4     High speed (tpd 10-50ns)     Military     CDIP | 16
CFP | 16
LCCC | 20