These positive-edge-triggered D-type flip-flops have a direct clear (CLR)\ input. The HC175 devices feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Bits (#)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Rating||Operating temperature range (C)|
|28||0.08||32||5.2||-5.2||No||Catalog||-40 to 85|
|SN54HC175||Samples not available||HC||2||6||4||
|28||0.08||32||5.2||-5.2||No||Military||-55 to 125|