100-pin (PZP) package image

TFP101APZP NOT RECOMMENDED FOR NEW DESIGNS

Panelbus DVI receiver 86 MHz, HSYNC fix

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Quality information

Rating Catalog
RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-3-260C-168 HR
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish / Ball material
  • MSL rating / Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Additional manufacturing information

Information included:

  • Fab location
  • Assembly location
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Export classification

*For reference only

  • US ECCN: EAR99

Packaging information

Package | Pins HTQFP (PZP) | 100
Operating temperature range (°C) 0 to 70
Package qty | Carrier 90 | JEDEC TRAY (10+1)

Features for the TFP101A

  • Supports XGA Resolution (Output Pixel Rates Up to 86 MHz)
  • Digital Visual Interface (DVI) Specification Compliant1
  • True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock
  • Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching
  • Skew Tolerant Up to One Pixel Clock Cycle
  • 4x Over-Sampling
  • Reduced Power Consumption – 1.8 V Core Operation With 3.3 V I/Os and Supplies2
  • Reduced Ground Bounce Using Time Staggered Pixel Outputs
  • Lowest Noise and Best Power Dissipation Using TI PowerPAD™ Packaging
  • Advanced Technology Using TI 0.18-µm EPIC-5™ CMOS Process
  • TFP101A Incorporates HSYNC Jitter Immunity3


PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
I2C is a licensed bus protocol from Phillips Semiconductor, Inc.

  1. The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays The TFP101 and TFP101A are compliant to the DVI Specification Rev. 1.0.
  2. The TFP101/101A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
  3. The TFP101A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.

Description for the TFP101A

The Texas Instruments TFP101 and TFP101A are TI PanelBus™ flat panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP101/101A finds applications in any design requiring high-speed digital interface.

The TFP101/101A supports display resolutions up to XGA in 24-bit true color pixel format. The TFP101/101A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground bounce.

PowerPAD™ advanced packaging technology results in best of class power dissipation, footprint, and ultra-low ground inductance.

The TFP101/101A combines PanelBus™ circuit innovation with TI’s advanced 0.18-µm EPIC-5™ CMOS process technology, along with TI PowerPAD™ package technology to achieve a reliable, low-powered, low noise, high-speed digital interface solution.

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Carrier options

You can choose different carrier options based on the quantity of parts, including full reel, custom reel, cut tape, tube or tray.

A custom reel is a continuous length of cut tape from one reel to maintain lot- and date-code traceability, built to the exact quantity requested. Following industry standards, a brass shim connects an 18-inch leader and trailer on both sides of the cut tape for direct feeding into automated assembly machines. TI includes a reeling fee for custom reel orders.

Cut tape is a length of tape cut from a reel. TI may fulfill orders using multiple strips of cut tapes or boxes to satisfy the quantity requested.

TI often ships tube or tray devices inside a box or in the tube or tray, depending on inventory availability. We pack all tapes, tubes or sample boxes according to internal electrostatic discharge and moisture-sensitivity-level protection requirements.

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Lot and date code selection may be available

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